512MB, 1GB, 2GB, 4GB (x72, DR, ECC) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM Unbuffered DIMM (UDIMM)
MT18HTF6472A – 512MB
MT18HTF12872A – 1GB
MT18HTF25672A – 2GB
MT18HTF51272A – 4GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• 240-pin, unbuffered dual in-line memory module
• Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
• 512MB (64 Meg x 72), 1GB (128 Meg x 72),
2GB (256 Meg x 72), 4GB (512 Meg x 72)
1
• V
DD
= V
DD
Q = +1.8V
• V
DDSPD
= +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Supports ECC error detection and correction
• Dual rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths (BL): 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Figure 1:
240-Pin UDIMM
(MO-237 R/C G or R/C B)
Height 30.0mm (1.18in)
Options
–
Commercial (0°C
≤
T
C
≤
+85°C)
• Package
–
240-pin DIMM (Pb-free)
• Frequency/CAS latency
–
2.5ns @ CL = 5 (DDR2-800)
3
–
2.5ns @ CL = 6 (DDR2-800)
3
–
3.0ns @ CL = 5 (DDR2-667)
–
3.75ns @ CL = 4 (DDR2-533)
–
5.0ns @ CL = 3 (DDR2-400)
• PCB height
–
30mm (1.18 in)
•
Operating temperature
2
Marking
None
Y
-80E
-800
-667
-53E
-40E
Notes: 1. Contact Micron for availability of the 4GB
device.
2. Contact Micron for industrial temperature
module offerings.
3. Not available in 512MB module density.
Table 1:
Speed
Grade
-80E
-800
-667
-53E
-40E
Key Timing Parameters
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
Data Rate (MT/s)
CL = 6
–
800
–
–
–
CL = 5
800
667
667
–
–
CL = 4
533
533
533
533
400
CL = 3
–
–
400
400
400
t
RCD
t
RP
t
RC
(ns)
12.5
15
15
15
15
(ns)
12.5
15
15
15
15
(ns)
55
55
55
55
55
PDF: 09005aef80e8ad4d/Source: 09005aef80e785e6
HTF18C64_128_256_512x72A.fm - Rev. G 1/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512MB, 1GB, 2GB, 4GB (x72, DR, ECC) 240-Pin DDR2 SDRAM UDIMM
Features
Table 2:
Addressing
512MB
Refresh count
Row address
Device bank address
Device page size per bank
Device configuration
Column address
Module rank address
1GB
2GB
8K
16K (A0–A13)
8 (BA0, BA1, BA2)
1KB
1Gb (128 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
4GB
8K
32K (A0–A14)
8 (BA0, BA1, BA2)
1KB
2Gb (256 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
8K
8K
8K (A0–A12)
16K (A0–A13)
4 (BA0, BA1)
4 (BA0, BA1)
1KB
1KB
256Mb (32 Meg x 8) 512Mb (64 Meg x 8)
1K (A0–A9
1K (A0–A9)
2 (S0#, S1#)
2 (S0#, S1#)
Table 3:
Part Numbers and Timing Parameters – 512MB Modules
Base device: MT47H32M8
2
, 256Mb DDR2 SDRAM
Module
Density
512MB
512MB
512MB
Module
Bandwidth
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
4-4-4
3-3-3
Part Number
1
MT18HTF6472AY-667__
MT18HTF6472AY-53E__
MT18HTF6472AY-40E__
Configuration
64 Meg x 72
64 Meg x 72
64 Meg x 72
Table 4:
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT47H64M8
2
, 512Mb DDR2 SDRAM
Module
Density
1GB
1GB
1GB
1GB
1GB
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
1
MT18HTF12872AY-80E__
MT18HTF12872AY-800__
MT18HTF12872AY-667__
MT18HTF12872AY-53E__
MT18HTF12872AY-40E__
Configuration
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
Table 5:
Part Numbers and Timing Parameters – 2GB Modules
Base device: MT47H128M8
2
, 1Gb DDR2 SDRAM
Module
Density
2GB
2GB
2GB
2GB
2GB
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
1
MT18HTF25672AY-80E__
MT18HTF25672AY-800__
MT18HTF25672AY-667__
MT18HTF25672AY-53E__
MT18HTF25672AY-40E__
Configuration
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
PDF: 09005aef80e8ad4d/Source: 09005aef80e785e6
HTF18C64_128_256_512x72A.fm - Rev. G 1/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB, 4GB (x72, DR, ECC) 240-Pin DDR2 SDRAM UDIMM
Features
Table 6:
Part Numbers and Timing Parameters – 4GB Modules
Base device: MT47H256M8
2
, 2Gb DDR2 SDRAM
Part Number
1
MT18HTF51272AY-80E__
MT18HTF51272AY-800__
MT18HTF51272AY-667__
MT18HTF51272AY-53E__
MT18HTF51272AY-40E__
Notes:
Module
Density
4GB
4GB
4GB
4GB
4GB
Configuration
512 Meg x 72
512 Meg x 72
512 Meg x 72
512 Meg x 72
512 Meg x 72
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
1. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT18HTF12872AY-667D4.
2. For component data sheets, refer to Micron’s Web site.
PDF: 09005aef80e8ad4d/Source: 09005aef80e785e6
HTF18C64_128_256_512x72A.fm - Rev. G 1/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB, 4GB (x72, DR, ECC) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 7:
Pin Assignments
240-Pin UDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
NC
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
31
DQ19
32
V
SS
33
DQ24
34
DQ25
35
V
SS
36 DQS3#
37
DQS3
38
V
SS
39
DQ26
40
DQ27
41
V
SS
42
CB0
43
CB1
44
V
SS
45 DQS8#
46
DQS8
47
V
SS
48
CB2
49
CB3
50
V
SS
51
V
DD
Q
52
CKE0
53
V
DD
1
NC/BA2
54
55
NC
56
V
DD
Q
57
A11
58
A7
59
V
DD
60
A5
Notes:
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
A4
V
DD
Q
A2
V
DD
V
SS
V
SS
V
DD
NC
V
DD
A10
BA0
V
DD
Q
WE#
CAS#
V
DD
Q
S1#
ODT1
V
DD
Q
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
240-Pin UDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
CK1
CK1#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
V
SS
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8
NC
V
SS
CB6
CB7
V
SS
V
DD
Q
CKE1
V
DD
NC
NC
V
DD
Q
A12
A9
V
DD
A8
A6
181
V
DD
Q 211
182
A3
212
183
A1
213
184
V
DD
214
185
CK0
215
186
CK0# 216
187
V
DD
217
188
A0
218
189
V
DD
219
190
BA1
220
191
V
DD
Q 221
192
RAS# 222
193
S0#
223
194
V
DD
Q 224
195
ODT0 225
2
NC/A13 226
196
197
V
DD
227
198
V
SS
228
199
DQ36 229
200
DQ37 230
201
V
SS
231
202
DM4
232
203
NC
233
204
V
SS
234
205
DQ38 235
206
DQ39 236
237
207
V
SS
208
DQ44 238
209
DQ45 239
240
210
V
SS
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK2
CK2#
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA0
SA1
1. Pin 54 is NC for 512MB and 1GB, or BA2 for 2GB and 4GB.
2. Pin 196 is NC for 512MB, or A13 for 1GB and 2GB and 4GB.
PDF: 09005aef80e8ad4d/Source: 09005aef80e785e6
HTF18C64_128_256_512x72A.fm - Rev. G 1/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB, 4GB (x72, DR, ECC) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments and Descriptions
Table 8:
Symbol
ODT0, ODT1
Pin Descriptions
Type
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Description
On-die termination:
ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS,
DQS#, and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
Clock:
CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Bank address inputs:
BA0–BA1/BA2 define to which device bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode
register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE
command.
Address inputs:
Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of
the memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE command.
Serial clock for presence-detect:
SCL is used to synchronize the presence-detect data
transfer to and from the module.
Presence-detect address inputs:
These pins are used to configure the presence-detect
device.
Data input mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with that input data, during a write access. DM is sampled on
both edges of DQS. Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins.
Data strobe:
Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only
used when differential data strobe mode is enabled via the LOAD MODE command.
Data input/output:
Bidirectional data bus.
Check bits.
Serial presence-detect data:
SDA is a bidirectional pin used to transfer addresses and
data into and out of the presence-detect portion of the module.
Power supply:
1.8V ±0.1V.
SSTL_18 reference voltage.
Ground.
Serial EEPROM positive power supply:
+1.7V to +3.6V.
No connect:
These pins should be left unconnected.
Reserved for future use.
CK0, CK0#,
CK1, CK1#,
CK2, CK2#
CKE0, CKE1
S0#, S1#
RAS#, CAS#, WE#
BA0, BA1
(512MB, 1GB)
BA0, BA1, BA2
(2GB, 4GB)
A0–A12
(512MB)
A0–A13
(1GB, 2GB)
A0–A14
(4GB)
SCL
SA0–SA2
DM0–DM8
Input
(SSTL_18)
Input
Input
Input
(SSTL_18)
DQS0–DQS8,
DQS0#–DQS8#
DQ0–DQ63
CB0–CB7
SDA
V
DD
/V
DD
Q
V
REF
V
SS
V
DDSPD
NC
RFU
I/O
(SSTL_18)
I/O
(SSTL_18)
I/O
(SSTL_18)
I/O
Supply
Supply
Supply
Supply
–
–
PDF: 09005aef80e8ad4d/Source: 09005aef80e785e6
HTF18C64_128_256_512x72A.fm - Rev. G 1/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
