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IS61NP25618-133B2I: 产品描述ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA119, PLASTIC, BGA-119; 产品类别存储存储; 文件大小133KB，共21页; 制造商ISSI(芯成半导体); 官网地址http://www.issi.com/

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IS61NP25618-133B2I概述

ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA119, PLASTIC, BGA-119

IS61NP25618-133B2I规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
Objectid	1959713729
零件包装代码	BGA
包装说明	PLASTIC, BGA-119
针数	119
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	4.2 ns
其他特性	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	133 MHz
I/O 类型	COMMON
JESD-30 代码	R-PBGA-B119
JESD-609代码	e0
长度	22 mm
内存密度	4718592 bit
内存集成电路类型	ZBT SRAM
内存宽度	18
功能数量	1
端子数量	119
字数	262144 words
字数代码	256000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	256KX18
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	QFP100,.63X.87
封装形状	RECTANGULAR
封装形式	GRID ARRAY
并行/串行	PARALLEL
电源	3.3 V
认证状态	Not Qualified
座面最大高度	2.41 mm
最大待机电流	0.01 A
最小待机电流	3.14 V
最大压摆率	0.305 mA
最大供电电压 (Vsup)	3.465 V
最小供电电压 (Vsup)	3.135 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	TIN LEAD
端子形式	BALL
端子节距	1.27 mm
端子位置	BOTTOM
宽度	14 mm

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IS61NP12832 IS61NP12836 IS61NP25618

IS61NLP12832 IS61NLP12836 IS61NLP25618

128K x 32, 128K x 36 and 256K x 18

PIPELINE 'NO WAIT' STATE BUS SRAM

FEATURES

•

100 percent bus utilization

No wait cycles between Read and Write

Internal self-timed write cycle

Individual Byte Write Control

Single R/W (Read/Write) control pin

Clock controlled, registered address,

data and control

Interleaved or linear burst sequence control

using MODE input

Three chip enables for simple depth expansion

and address pipelining for TQFP

Power Down mode

Common data inputs and data outputs

CKE

pin to enable clock and suspend operation

JEDEC 100-pin TQFP and 119 PBGA packages

Single +3.3V power supply (± 5%)

NP Version: 3.3V I/O Supply Voltage

NLP Version: 2.5V I/O Supply Voltage

Industrial temperature available

ISSI

NOVEMBER 2002

DESCRIPTION

The 4 Meg 'NP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

network and communications customers. They are

organized as 131,072 words by 32 bits, 131,072 words

by 36 bits and 262,144 words by 18 bits, fabricated with

ISSI

's advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE

is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when

is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-150

3.8

6.7

150

-133

4.2

7.5

133

-100

100

Units

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. B

11/21/02

IS61NP25618-133B2I

IS61NP25618-133B2I概述

IS61NP25618-133B2I规格参数

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