Advance Information
MPC8245EC
Rev. 5.1, 2/2004
MPC8245
Integrated Processor
Hardware Specifications
The MPC8245 combines a PowerPC™ MPC603e core with a PCI bridge. The PCI support on
the MPC8245 allows system designers to rapidly design systems using peripherals already
designed for PCI and the other standard interfaces. The MPC8245 also integrates a
high-performance memory controller that supports various types of ROM and SDRAM. The
MPC8245 is the second of a family of products that provide system-level support for industry
standard interfaces with a MPC603e processor core.
This hardware specification describes pertinent electrical and physical characteristics of the
MPC8245. For functional characteristics of the processor, refer to the
MPC8245 Integrated
Processor User’s Manual
(MPC8245UM).
This hardware specification contains the following topics:
Topic
Section 1, “Overview”
Section 2, “Features”
Section 3, “General Parameters”
Section 4, “Electrical and Thermal Characteristics”
Section 5, “Package Description”
Section 6, “PLL Configurations”
Section 7, “System Design Information”
Section 8, “Document Revision History”
Section 9, “Ordering Information”
Page
1
3
5
5
32
40
44
57
60
To locate any published errata or updates for this document, refer to the website at
http://www.motorola.com/semiconductors
1
Overview
The MPC8245 integrated processor is comprised of a peripheral logic block and a 32-bit
superscalar MPC603e core, as shown in Figure 1.
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Overview
MPC8245
Additional Features:
• Prog I/O with Watchpoint
• JTAG/COP Interface
• Power Management
Processor Core Block
Processor
PLL
(64-Bit) Two-Instruction Fetch
Branch
Processing
Instruction Unit
Unit
(BPU)
(64-Bit) Two-Instruction Dispatch
System
Register
Unit
(SRU)
Integer
Unit
(IU)
Load/Store
Unit
(LSU)
Floating-
Point
Unit
(FPU)
64-Bit
Data
MMU
16-Kbyte
Data
Cache
Instruction
MMU
16-Kbyte
Instruction
Cache
Peripheral Logic Bus
Peripheral Logic Block
Message
Unit
(with I
2
O)
DMA
Controller
Address
(32-Bit)
Central
Control
Unit
Performance
Monitor
I
2
C
I
2
C
Controller
PIC
Interrupt
Controller/
Timers
DUART
DLL
Peripheral Logic
PLL
Configuration
Registers
PCI Bus
Interface Unit
Address
Translator
PCI
Arbiter
Data (64-Bit)
Data Path
ECC Controller
Data Bus
(32- or 64-Bit)
with 8-Bit Parity
or ECC
Memory/ROM/
PortX Control/Address
Memory
Controller
SDRAM_SYNC_IN
SDRAM Clocks
PCI_SYNC_IN
5 IRQs/
16 Serial
Interrupts
Watchpoint
Facility
Fanout
Buffers
OSC_IN
PCI Bus
Clocks
32-Bit
PCI Interface
Five
Request/Grant
Pairs
Figure 1. MPC8245 Block Diagram
2
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Features
The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART),
memory controller, DMA controller, PIC interrupt controller, a message unit (and I
2
O interface), and an I
2
C
controller. The processor core is a full-featured, high-performance processor with floating-point support,
memory management, a 16-Kbyte instruction cache, a 16-Kbyte data cache, and power management
features. The integration reduces the overall packaging requirements and the number of discrete devices
required for an embedded system.
The MPC8245 contains an internal peripheral logic bus that interfaces the processor core to the peripheral
logic. The core can operate at a variety of frequencies, allowing the designer to trade off performance for
power consumption. The processor core is clocked from a separate PLL that is referenced to the peripheral
logic PLL. This allows the microprocessor and the peripheral logic block to operate at different frequencies
while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on
memory data bus width) and a 32-bit address bus along with control signals that enable the interface
between the processor and peripheral logic to be optimized for performance. PCI accesses to the MPC8245
memory space are passed to the processor bus for snooping when snoop mode is enabled.
The processor core and peripheral logic are general-purpose in order to serve a variety of embedded
applications. The MPC8245 can be used as either a PCI host or PCI agent controller.
2
•
Features
Processor core
— High-performance, superscalar processor core
— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit
(LSU), system register unit (SRU), and branch processing unit (BPU)
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 caches—Entire cache or on a per-way basis up to three of four ways
— Dynamic power management—Supports 60x nap, doze, and sleep modes
Peripheral logic
— Peripheral logic bus
– Supports various operating frequencies and bus divider ratios
– 32-bit address bus, 64-bit data bus
– Supports full memory coherency
– Decoupled address and data buses for pipelining of peripheral logic bus accesses
– Store gathering on peripheral logic bus-to-PCI writes
— Memory interface
– Supports up to 2 Gbytes of SDRAM memory
– High-bandwidth data bus (32- or 64-bit) to SDRAM
– Programmable timing supporting SDRAM
– Supports one to eight banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices
– Write buffering for PCI and processor accesses
– Supports normal parity, read-modify-write (RMW), or ECC
– Data-path buffering between memory interface and processor
Major features of the MPC8245 are as follows:
•
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3
Features
—
—
—
—
—
—
– Low-voltage TTL logic (LVTTL) interfaces
– 272 Mbytes of base and extended ROM/Flash/PortX space
– Base ROM space supports 8-bit data path or same size as the SDRAM data path (32- or
64-bit)
– Extended ROM space supports 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data
path
– PortX: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
programmable address strobe timing, data ready input signal (DRDY), and 4 chip selects
32-bit PCI interface
– Operates up to 66 MHz
– PCI 2.2-compatible
– PCI 5.0-V tolerance
– Support for dual address cycle (DAC) for 64-bit PCI addressing (master only)
– Support for PCI locked accesses to memory
– Support for accesses to PCI memory, I/O, and configuration spaces
– Selectable big- or little-endian operation
– Store gathering of processor-to-PCI write and PCI-to-memory write accesses
– Memory prefetching of PCI read accesses
– Selectable hardware-enforced coherency
– PCI bus arbitration unit (five request/grant pairs)
– PCI agent mode capability
– Address translation with two inbound and outbound units (ATU)
– Some internal configuration registers accessible from PCI
Two-channel integrated DMA controller (writes to ROM/PortX not supported)
– Supports direct mode or chaining mode (automatic linking of DMA transfers)
– Supports scatter gathering—Read or write discontinuous memory
– 64-byte transfer queue per channel
– Interrupt on completed segment, chain, and error
– Local-to-local memory
– PCI-to-PCI memory
– Local-to-PCI memory
– PCI memory-to-local memory
Message unit
– Two doorbell registers
– Two inbound and two outbound messaging registers
– I
2
O message interface
I
2
C controller with full master/slave support that accepts broadcast messages
Programmable interrupt controller (PIC)
– Five hardware interrupts (IRQs) or 16 serial interrupts
– Four programmable timers with cascade
Two (dual) universal asynchronous receiver/transmitters (UARTs)
4
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
General Parameters
•
•
— Integrated PCI bus and SDRAM clock generation
— Programmable PCI bus and memory interface output drivers
System-level performance monitor facility
Debug features
— Memory attribute and PCI attribute signals
— Debug address signals
— MIV signal—Marks valid address and data bus cycles on the memory bus
— Programmable input and output signals with watchpoint capability
— Error injection/capture on data path
— IEEE 1149.1 (JTAG)/test interface
3
General Parameters
Technology
Die size
Transistor count
Logic design
Packages
Core power supply
0.25-µm CMOS, five-layer metal
49.2 mm
2
4.5 million
Fully-static
Surface-mount 352 tape ball grid array (TBGA)
1.8 V ± 100 mV DC (only for 266- and 300-MHz parts)
2.0 V ± 100 mV DC (for 266-, 300-, 333-, and 350-MHz parts)
(nominal, see Table 2 for details and recommended operating conditions)
3.0- to 3.6-V DC
The following list provides a summary of the general parameters of the MPC8245:
I/O power supply
4
Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8245.
4.1 DC Electrical Characteristics
This section covers ratings, conditions, and other DC electrical characteristics.
4.1.1 Absolute Maximum Ratings
The tables in this section describe the MPC8245 DC electrical characteristics. Table 1 provides the absolute
maximum ratings.
Table 1. Absolute Maximum Ratings
Characteristic
1
Supply voltage—CPU core and peripheral logic
Supply voltage—memory bus drivers
Supply voltage—PCI and standard I/O buffers
Supply voltage—PLLs
Symbol
V
DD
GV
DD
OV
DD
AV
DD
/AV
DD
2
Range
–0.3 to 2.1
–0.3 to 3.6
–0.3 to 3.6
–0.3 to 2.1
Unit
V
V
V
V
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
5
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