Analog Frequency Multiplier
VCXO Family of Products
PRODUCT DESCRIPTION
PhaseLink’s Analog Frequency Multiplier
TM
(AFMs)
are the industry’s first ‘Balanced Oscillator’ utilizing
analog multiplication of the fundamental frequency
(at double or quadruple frequency), combined with
an attenuation of the fundamental of the reference
crystal, without the use of a phase locked loop, in
CMOS technology.
PhaseLink’s patent pending PL56X family of AFM
products can achieve up to 800 MHz output
frequency with practically no jitter or phase noise
deterioration. In addition, the low frequency input
crystal requirement makes the AFMs the most
affordable high performance timing source in the
market.
PL560-XX family of products utilize a low-power
CMOS technology and are housed in a 16-pin
(T)SSOP, and 16-pin 3x3 QFN.
FEATURES
•
•
•
•
•
•
Non Phase Locked Loop frequency multiplication
Input frequency from 30-200 MHz
Output frequency from 60-800-MHz
Low Phase noise and jitter (equivalent to fundamental
crystal at the output frequency)
Unbeatably low jitter
o
RMS phase jitter < 0.25ps (12kHz-20MHz)
o
RMS period jitter < 2.5 ps
Low Phase Noise
o
-142 dBc/Hz @100kHz Offset from 155.52MHz
o
-150 dBc/Hz @10MHz Offset from 155.52MHz
High linearity pull range (typ. 5%)
+/- 120 PPM pullability VCXO
Low input frequency eliminates the need for
expensive crystals
Differential output levels (PECL, LVDS), or single-
ended CMOS
Single 2.5V or 3.3V +/- 10% power supply
Optional industrial temperature range (-40°C to
+85°C)
Available in 16-pin (T) SSOP, and 3x3 QFN
•
•
•
•
•
•
•
Figure 1: 2x AFM Phase Noise at 311.04MHz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 02/10/05 Page 1
Analog Frequency Multiplier
VCXO Family of Products
L2X
OECTRL
X IN
O s c illa to r
A m p lifie r
F re q u e n c y
X2
F re q u e n c y
X4
VC on
QBAR
Q
XOUT
O n ly r e q u ir e d in x 4 d e s ig n s
L4X
Figure 2: Overall VCXO AFM Block Diagram
Figure 3 shows the jitter histogram of the 2x Analog Frequency Multiplier at 155.52MHz, while figure 4 shows the very low
rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance.
Figure 3: Jitter Histogram at 311.04 MHz
Analog Frequency Multiplier (2x)
with 155.52MHz crystal
Figure 4: Spectrum Analysis at 311.04 MHz
Analog Frequency Multiplier (2x)
with sub-harmonic below –72 dBc
OE LOGIC SELECTION
OUTPUT
OESEL
0 (Default)
PECL
1
0 (Default)
LVDS or CMOS
1
OE
0 (Default)
1
0
1 (Default)
0
1 (Default)
0 (Default)
1
Output State
Enabled
Tri-state
Tri-state
Enabled
Tri-state
Enabled
Enabled
Tri-state
OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. Internally set to default through pull-down / -up.
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev.:03-22-05 Page 2
Analog Frequency Multiplier
VCXO Family of Products
PRODUCT SELECTION GUIDE
FREQUENCY VERSUS PHASE NOISE PERFORMANCE
Part
Number
Input
Frequency
Range (MHz)
Analog
Frequency
Multiplication
Factor
4
4
4
4
4
2
2
2
2
2
Output
Frequency
Range (MHz)
Phase Noise AT Frequency Offset From Carrier (dBc/Hz)
Output
Type
Carrier
Freq.
(MHz)
622.08
622.08
155.52
155.52
155.52
155.52
155.52
155.52
311.04
311.04
10
KHz
-130
-130
-128
-128
-128
-138
-138
-138
-135
-135
100
KHz
-137
-137
-142
-142
-142
-142
-142
-142
-142
-142
10
MHz
-150
-150
-150
-150
-150
-149
-149
-149
-151
-151
10 Hz
-55
-55
-50
-50
-50
-65
-65
-65
-60
-60
100 Hz
-85
-85
-82
-82
-82
-95
-95
-95
-85
-85
1 KHz
-110
-110
-110
-110
-110
-122
-122
-122
-112
-112
1 MHz
-148
-148
-148
-148
-148
-148
-148
-148
-150
-150
PL560-08
PL560-09
PL560-37
PL560-38
PL560-39
PL560-47
PL560-48
PL560-49
PL560-68
PL560-69
75 - 200
75 - 200
30 - 80
30 - 80
30 - 80
30 - 80
30 - 80
30 - 80
75 - 200
75 - 200
300 - 800
300 - 800
120 - 320
120 - 320
120 - 320
60 - 160
60 - 160
60 - 160
150 - 400
150 - 400
PECL
LVDS
CMOS
PECL
LVDS
CMOS
PECL
LVDS
PECL
LVDS
Phase Noise numbers were obtained using Agilent 5500.
FREQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE
Jitter
Calc.
Freq.
(MHz)
622
622
155
155
155
155
155
155
311
311
RMS Period
Jitter
(Ps)
Peak to Peak
Period Jitter
(Ps)
RMS Accumulated
(L.T.) Jitter (Ps)
Phase Jitter
(12 KHz-20MHz)
(Ps)
Typ.
0.09
0.09
0.25
0.25
0.25
0.25
0.25
0.27
0.18
0.18
Spectral Specifications / Sub-harmonic Content
(dB), Frequency (MHz)
Carrier @
@
@
@
@
@
Max. Freq. -75%
-50% -25% +25% +50% +75%
(Fc)
(Fc)
(Fc) (Fc)
(Fc) (Fc) (Fc)
622
622
155.52
155.52
155.52
155.52
155.52
155.52
311.04
311.04
-50
-50
-75
-75
-75
-50
-50
-62
-62
-62
-68
-68
-68
-72
-72
-45
-45
-47
-47
-47
-47
-65
-65
-65
-68
-68
-68
-85
-85
-55
-55
-75
-75
-75
Part
Number
Min. Typ. Max. Min. Typ. Max. Min. Typ.
4
4
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
6
6
3
3
3
3
3
3
3
3
25
25
18
18
18
18
18
18
18
18
30
30
20
20
20
20
20
20
20
20
Max. Min.
6
6
3
3
3
3
3
3
3
3
PL560-08
PL560-09
PL560-37
PL560-38
PL560-39
PL560-47
PL560-48
PL560-49
PL560-68
PL560-69
Note:
Wavecrest Data 10,000 hits. No Filtering was used in Jitter Calculations.
Agilent 5500 was used for Phase Jitter Calculations.
Spectral Specifications were obtained using Agilent E7401A.
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev.:03-22-05 Page 3
Analog Frequency Multiplier
VCXO Family of Products
CRYSTAL SPECIFICATIONS AND BOARD LAYOUT CONSIDERATIONS
BOARD LAYOUT CONSIDERATIONS
AFM IC
XTA
XIN (Pin # 4)
XOUT (Pin # 5)
AFM IC
XTAL
Ceramic
SMD
XIN (Pin # 4)
XOUT (Pin # 5)
To minimize parasitic effects, and improve performance:
•
Place the crystal as close as possible to the IC.
•
Make the board traces that are connected to the crystal pins symmetrical.
•
The board trace symmetry is important, as it reduces the negative parasitic effects, for a clean frequency multiplication with low
jitter. Parasitic have negative effect on frequency pulling of a VCXO and jitter.
CRYSTAL SPECIFICATIONS & TUNING PERFORMANCE
CRYSTAL SPECIFICATIONS
PART
NUMBER
CRYSTAL
RESONATOR
FREQUENCY
(FXIN)
TUNING PERFORMANCE
ESR
(R
E
)
Max.
CRYSTAL
FREQ
(MHz)
155.52
5pF
30
Ω
155.52
30.72
1.8pF
2.8pF
4.5pF
5.1pF
5.3pF
2.0pF
5.7fF
12.4fF
19.1fF
20.9fF
25.6fF
6.7fF
316
228
236
242
207
305
-134 ppm
-167ppm
-163ppm
-131ppm
-157ppm
-92ppm
+87 ppm
+176ppm
+167ppm
+98ppm
+141ppm
+110ppm
MOD
E
CL (xtal)
CONDI-
TIONS
At
Vcon
=
1.65V
TYP.
CRYSTAL
C0
3.0pF
C1
12.2fF
C0/C1
245
TUNING (Typical)
VC:
1.65V
0V
-145 ppm
VC:
1.65V 3.4V
+108 ppm
PL560-08/09
PL560-68/69
75~200MHz
Funda-
mental
PL560-
37/38/39
PL560-
47/48/49
30~80MHz
Funda-
mental
At
Vcon
=
1.65V
30.72
5pF
30
Ω
38.88
38.88
77.76
Note:
Non specified parameters can be chosen as standard values from crystal suppliers.
CL ratings larger than 5pF require a crystal frequency adjustment. Request detailed crystal specifications from PhaseLink.
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev.:03-22-05 Page 4
Analog Frequency Multiplier
VCXO Family of Products
VOLTAGE CONTROL SPECIFICATION
PARAMETERS
VCXO Stabilization Time
VCXO Tuning Range
CLK output pullability
Linearity
VCON input impedance
VCON modulation BW
0V < VCON < 3.3V, -3dB
130
25
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
XTAL C
0
/C
1
<300
VCON= 1.65V
±
1.65V
XTAL C
0
/C
1
<300
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
200
±100
±120
ppm
5
10
%
kΩ
kHz
EXTERNAL COMPONENT VALUES
INDUCTOR VALUE OPTIMIZATION
The required inductor value(s) for the best performance depends on the operating frequency, and the board
layout specifications. The listed values in this datasheet are based on the calculated parasitic values from
PhaseLink’s evaluation board design (Gerber file available upon request). These inductor values provide the user
with a starting point to determine the optimum inductor values. Additional fine-tuning may be required to
determine the optimal solution.
To assist with the inductor value optimization, PhaseLink has developed the “AFM Tuning Assistant” software.
You can download this software from PhaseLink’s web site (www.phaselink.com). The software consists of two
worksheets. The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second
worksheet (named L4) is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value.
For those designs using PhaseLink’s recommended board layout, you can use the “AFM Tuning Assistant” to
determine the optimum values for the required inductors. This software is developed based on the parasitic
information from PhaseLink’s board layout and can be used to determine the required inductor and parallel
capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their
design, we recommend to use the parasitic information of their board layout to calculate the optimized inductor
values. Please use the following fine tuning procedure:
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev.:03-22-05 Page 5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
