Very low Jitter and Phase Noise (< 40ps Pk-Pk typical)
Output frequency up to 375MHz CMOS.
Supports differential CMOS output to produce PECL,
LVDS inputs.
Crystal inputs:
o
Fundamental crystal: 10MHz-30MHz
o
3
RD
overtone crystal: Up to 75MHz
o
Reference input: Up to 200MHz
Accepts <1.0V reference signal input voltage
One programmable I/O pin can be configured as
Output Enable (OE), or Frequency Selection input
(FSEL), or Reference clock.
Single 3.3V ± 10% power supply
Operating temperature range from -40°C to 85°C
Available in 8-pin MSOP/SOIC, 6-pin SOT Green/
RoHS compliant packages.
PIN CONFIGURATION
XIN/FIN
GND
CLK0
CLK1
1
8
XOUT
CLK2, OE, FSEL
DNC
VDD
PL611-30
SOP-8
MSOP-8
2
3
4
7
6
5
•
•
•
•
•
DESCRIPTION
The PL611-30 is a low-cost general purpose frequency synthesizer and a member of PhaseLink’s Factory
Programmable ‘Quick Turn Clock (QTC)’ family. PhaseLink’s PL611-30 product family can generate any output
frequency up to 375 MHz from fundamental crystal input between 10 MHz - 30 MHz, or a 3rd overtone crystal of
up to 75Mhz. The PL611-30 produces differential CMOS outputs to support PECL, LVDS, and CMOS inputs.
BLOCK DIAGRAM
XIN/FIN
XOUT
Xtal
OSC
FRef
.
R- counter
Phase
Detector
M-counter
( 6 -bit)
Charge
Pump
Loop
Filter
Programming
Logic
FSEL
OE
CLoad
F
VCO
= F
Ref.
* (2 * M /R)
P-counter
(5-bit)
VCO
F
Out
= F
VCO
/ (2 * P)
CLK[0:1]
CLK2
Programmable Function
/1, /2
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 03/03/05 Page 1
Preliminary
PL611-30
Programmable Quick Turn Clock
T M
KEY PROGRAMMING PARAMETERS
CLK[ 0:2 ]
Output Frequency
Fout = FIN * M / (R * P)
where M= 6 bit
R= 1
P= 5 bit
1. CLK[0:1]= VCO / 2 * P
2. CLK[2]= FIN or FIN/2
Output Drive
Strength
Std: 10mA
(default)
High: 24mA
Crystal
Load
Programmable
Input/Output (pin #7)
# of
Register
Banks
2
Charge-Pump
Current
4 levels of pump
current setting
+/- 200ppm One output pin can be
tuning.
configured as
1. CLK2 = FIN or FIN/2
2. FSEL - input
3. OE - input
PIN DESCRIPTION
Name
XIN/FIN
GND
CLK[0:1]
VDD
DNC
Pin #
(M)SOP-8
1
2
3,4
5
6
Type
I
P
O
P
-
Description
Crystal or Reference input pin
GND connection
Programmable Clock Output [note:CLK0=~CLK1]
VDD connection
Do No Connect
This programmable I/O pin can be configured as CLK2
(FIN
or FIN/2)
output, or OE input, or Frequency
Selection (FSEL) input pin. This pin has an internal 60K
pull up resistor.
State
0
1 (default)
OE
Tristate
CLK[0:1]
Normal
mode
FSEL
Select Bank ’0’
ROM
Select Bank ‘1’
ROM
CLK2, OE, FSEL
7
B
XOUT
8
O
Crystal output pin
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 03/03/05 Page 2
Preliminary
PL611-30
Programmable Quick Turn Clock
T M
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Data Retention @ 85º C
Soldering Temperature
Storage Temperature
Ambient Operating Temperature*
T
S
-65
-40
SYMBOL
V
DD
V
I
V
O
MIN.
MAX.
4.6
V
DD
+
0.5
V
DD
+
0.5
240
150
+85
UNITS
V
V
V
Years
°C
°C
°C
-
0.5
-
0.5
-
0.5
10
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency
CONDITIONS
Fundamental Crystal
3
rd
Overtone Crystal
At power-up (after VDD increases over
1.62V)
Frequency vs. VDD+/-10%
15pF Load, 10/90%VDD, Standard drive
15pF Load, 10/90%VDD, High drive
15pF Load, 90/10%VDD, Standard drive
15pF Load, 90/10%VDD, High drive
At VDD/2
Equal loading (15 pF). Equal frequency
& drive strength
With capacitive decoupling between VDD
and GND. Operating only one output.
MIN.
10
TYP.
MAX.
30
75
10
UNITS
MHz
MHz
ms
ppm
ns
ns
ns
ns
%
ps
Settling Time
VDD Sensitivity
Output Rise Time
-2
2.5
1.0
2.5
1.0
45
50
2
3.5
1.5
3.5
1.5
55
500
Output Fall Time
Duty Cycle
Max. output skew between
same frequency clocks
Period Jitter, peak-to-peak*
(measured from 10,000
samples)
40
ps
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 03/03/05 Page 3
Preliminary
PL611-30
Programmable Quick Turn Clock
T M
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic,
with Loaded Outputs
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current
Short-circuit Current
SYMBOL
I
DD
V
DD
V
OL
V
OH
I
OSD
I
OHD
I
S
CONDITIONS
At 10MHz, load=15pF
MIN.
TYP.
MAX.
15
UNITS
mA
V
V
V
2.25
I
OL
= +4mA (Standard drive)
I
OH
= -4mA (Standard drive)
V
OL
= 0.4V, V
OH
= 2.4V (Standard
drive)
V
OL
= 0.4V, V
OH
= 2.4V (High Drive)
V
DD
– 0.4
10
24
± 50
3.63
0.4
mA
mA
mA
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
3
rd
Overtone Crystal Resonator Frequency
Crystal Loading Rating
(The IC can be programmed for any value in this range.)
Maximum Sustainable Drive Level
Operating Drive Level
Crystal Shunt Capacitance
Effective Series Resistance, Fundamental, 10-30MHz
Effective Series Resistance, 3
rd
Overtone, 30-50MHz
[CO< 4pF, C
L
=5pF/8pF]
Effective Series Resistance, 3
rd
Overtone, 50-65MHz,
[CO< 4pF, C
L
=5pF/8pF]
Effective Series Resistance, 3
rd
Overtone, 65-75MHz
[CO< 4pF, C
L
=5pF/8pF
Note:
A detailed crystal specification document is also available for this part
SYMBOL
F
XIN
F
XIN
C
L (xtal)
MIN.
10
TYP.
MAX.
30
75
UNITS
MHz
MHz
pF
µW
µW
pF
Ω
Ω
Ω
Ω
5
20
500
100
C0
R
S
ESR
ESR
ESR
6
30
100/70
60/40
45/30
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 03/03/05 Page 4
Preliminary
PL611-30
Programmable Quick Turn Clock
T M
Figure 1 below describes how to terminate the differential CMOS outputs of PhaseLink’s PL611-30 Programmable QTC clock
for use with PECL or LVDS inputs.
The unique feature of differential CMOS outputs allows great flexibility for board designers. By standardizing on one termination
scheme you can use the PL611-30 for all your LVDS and PECL clock requirements up to 375MHz.
+3.3V
CMOS Output
R1
50Ω line
R2
Input
R3
Complementary
CMOS Output
R1
50Ω line
R3
Complementary
Input
PECL LVDS
2.35V 1.40V
1.59V 1.10V
3.3V
0V
Component selection
For PECL input
For LVDS input
R1 = 130Ω
R2 = 82Ω
R3 = 130Ω
R1 = 360Ω
R2 = 82Ω
R3 = 130Ω
R2
+3.3V
Notes:
Place R1 as close to the CMOS outputs as
possible.
Place R2 and R3 as close to the PECL/LVDS
inputs as possible.
Figure 1
The above layout allows the PL611-30 to drive either a PECL or LVDS input by simply changing the value of R1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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