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PLC42VA12A

产品描述CMOS programmable multi-function PLD 42 】 105 】 12
产品类别可编程逻辑器件    可编程逻辑   
文件大小195KB,共20页
制造商Philips Semiconductors (NXP Semiconductors N.V.)
官网地址https://www.nxp.com/
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PLC42VA12A概述

CMOS programmable multi-function PLD 42 】 105 】 12

PLC42VA12A规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Philips Semiconductors (NXP Semiconductors N.V.)
包装说明QCCJ, LDCC28,.5SQ
Reach Compliance Codeunknow
架构PLS-TYPE
最大时钟频率14.9 MHz
JESD-30 代码S-PQCC-J28
JESD-609代码e0
输入次数42
输出次数12
产品条款数105
端子数量28
最高工作温度70 °C
最低工作温度
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装等效代码LDCC28,.5SQ
封装形状SQUARE
封装形式CHIP CARRIER
电源5 V
认证状态Not Qualified
标称供电电压5 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式J BEND
端子节距1.27 mm
端子位置QUAD

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Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42
×
105
×
12)
PLC42VA12
DESCRIPTION
The new PLC42VA12 CMOS PLD from
Philips Semiconductors exhibits a unique
combination of the two architectural concepts
that revolutionized the PLD marketplace.
The Philips Semiconductors unique Output
Macro Cell (OMC) embodies all the
advantages and none of the disadvantages
associated with the “V” type Output Macro
Cell devices. This new design, combined with
added functionality of two programmable
arrays, represents a significant advancement
in the configurability and efficiency of
multi-function PLDs.
The most significant improvement in the
Output Macro Cell structure is the
implementation of the register bypass
function. Any of the 10 J-K/D registers can be
individually bypassed, thus creating a
combinatorial I/O path from the AND array to
the output pin. Unlike other “V” type devices,
the register in the PLC42VA12 Macro Cell
remains fully functional as a buried register.
Both the combinatorial I/O and buried register
have separate input paths (from the AND
array). In most V-type architectures, the
register is lost as a resource when the cell is
configured as a combinatorial I/O. This
feature provides the capability to operate the
buried register independently from the
combinatorial I/O.
The PLC42VA12 is an EPROM-based CMOS
device. Designs can be generated using
Philips Semiconductors SNAP PLD design
software packages or one of several other
commercially available JEDEC standard PLD
design software packages.
FEATURES
High-speed EPROM-based CMOS
Multi-Function PLD
Super set of 22V10, 32VX10 and
20RA10 PAL® ICs
PIN CONFIGURATIONS
FA and N Pack-
ages
I0/CLK
I1
I2
I3
I4
I5
I6
I7
I8
1
2
3
4
5
6
7
8
9
24 V
CC
23 M9
22 M8
21 M7
20 M6
19 M5
18 M4
17 M3
16 M2
15 M1
14 M0
13 I9/OE
Two fully programmable arrays eliminate
“P-term Depletion”
Up to 64 P-terms per OR function
Improved Output Macro Cell Structure
Individually programmable as:
* Registered Output with feedback
* Registered Input
* Combinatorial I/O with Buried Register
* Dedicated I/O with feedback
* Dedicated Input (combinatorial)
Bypassed Registers are 100% functional
with separate input and feedback paths
Individual Output Enable control
functions
* From pin or AND array
B0 10
B1 11
GND 12
Reprogrammable – 100% tested for
programmability
N = Plastic DIP (300mil-wide)
FA = Ceramic DIP with Quartz Window (300mil-wide)
Eleven clock sources
Register Preload and Diagnostic Test Mode
Features
A Package
I2
4
I0/
I1 CLK N/C V
CC
M9 M8
3
2
1
28
27
26
25 M7
24 M6
23 M5
22 N/C
21 M4
20 M3
19 M2
12
13
14
15
16
17
18
Security fuse
APPLICATIONS
Synchronous
Asynchronous
I3
I4
I5
N/C
I6
5
6
7
8
9
Mealy or Moore State Machines
Multiple, independent State Machines
10-bit ripple cascade
Sequence recognition
Bus Protocol generation
Industrial control
A/D Scanning
I7 10
I8 11
B0 B1 GND N/C I9/ M0 M1
OE
A = Plastic Leaded Chip Carrier (450mil-square)
ORDERING INFORMATION
DESCRIPTION
24-Pin Ceramic Dual In-Line with window,
Reprogrammable (300mil-wide)
24-Pin Plastic Dual In-Line,
One Time Programmable (300mil-wide)
28-Pin Plastic Leaded Chip Carrier,
One Time Programmable (450mil-wide)
ORDER CODE
PLC42VA12FA
PLC42VA12N
PLC42VA12A
DRAWING NUMBER
1478A
0410D
0401F
PAL is a registered trademark of Advanced Micro Devices, Inc.
October 22, 1993
73
853–1414 11164

PLC42VA12A相似产品对比

PLC42VA12A PLC42VA12FA PLC42VA12 PLC42VA12N
描述 CMOS programmable multi-function PLD 42 】 105 】 12 CMOS programmable multi-function PLD 42 】 105 】 12 CMOS programmable multi-function PLD 42 】 105 】 12 CMOS programmable multi-function PLD 42 】 105 】 12
是否Rohs认证 不符合 不符合 - 不符合
厂商名称 Philips Semiconductors (NXP Semiconductors N.V.) Philips Semiconductors (NXP Semiconductors N.V.) - Philips Semiconductors (NXP Semiconductors N.V.)
包装说明 QCCJ, LDCC28,.5SQ DIP, DIP24,.3 - DIP, DIP24,.3
Reach Compliance Code unknow unknow - unknow
架构 PLS-TYPE PLS-TYPE - PLS-TYPE
最大时钟频率 14.9 MHz 14.9 MHz - 14.9 MHz
JESD-30 代码 S-PQCC-J28 R-XDIP-T24 - R-PDIP-T24
JESD-609代码 e0 e0 - e0
输入次数 42 42 - 42
输出次数 12 12 - 12
产品条款数 105 105 - 105
端子数量 28 24 - 24
最高工作温度 70 °C 70 °C - 70 °C
封装主体材料 PLASTIC/EPOXY CERAMIC - PLASTIC/EPOXY
封装代码 QCCJ DIP - DIP
封装等效代码 LDCC28,.5SQ DIP24,.3 - DIP24,.3
封装形状 SQUARE RECTANGULAR - RECTANGULAR
封装形式 CHIP CARRIER IN-LINE - IN-LINE
电源 5 V 5 V - 5 V
认证状态 Not Qualified Not Qualified - Not Qualified
标称供电电压 5 V 5 V - 5 V
表面贴装 YES NO - NO
技术 CMOS CMOS - CMOS
温度等级 COMMERCIAL COMMERCIAL - COMMERCIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb)
端子形式 J BEND THROUGH-HOLE - THROUGH-HOLE
端子节距 1.27 mm 2.54 mm - 2.54 mm
端子位置 QUAD DUAL - DUAL

 
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