The PLL1700 can generate four systems clocks from a
27MHz reference input frequency.
The device gives customers both cost and space savings
by eliminating external components and enables cus-
tomers to achive the very low jitter performance needed
for high performance audio digital-to-analog convert-
ers (DAC) and/or analog-to-digital converters (ADC).
The PLL1700 is ideal for MPEG-2 applications which
use a 27MHz master clock such as DVD players, DVD
add-on cards for multimedia PCs, digital HDTV sys-
tems, and set-top boxes.
MODE
ML
MC
MD
V
DDP
GNDP V
DDB
GNDB V
DD
GND
Mode
Control
I/F
RST
Reset
Power Supply
PLL2
XT1
OSC
XT2
PLL1
Counter Q
Counter P
MCKO MCKO
SCKO1
SCKO2
SCKO3
SCKO4
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
NOTES: (1) ML, MC, MD, MODE, RST (Schmitt-trigger input with internal pull-down resistor). (2) XT1, when an external 27MHz clock is used, the buffer ICs, such
as 74HC04, are recommended to interface to XT1. (3) MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1. (4) Jitter performance is specified as standard
deviation of jitter under 27MHz crystal oscillation. (5) When SCKO2 is set to double rate clock output, its duty cycle is 33%. (6) f
M
= 27MHz crystal oscillation, no
load on MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
PLL1700
2
PIN CONFIGURATION
TOP VIEW
SSOP
PIN ASSIGNMENTS
PIN
1
NAME
ML/SR0
I/O
IN
FUNCTION
Latch Enable for Software Mode/Sampling Rate
Selection for Hardware Mode. When MODE pin
is LOW, ML is selected.
(1)
Mode Control Select. When this pin is HIGH,
device is operated in hardware mode using SR0
(pin 1), FS0 (pin 19), and FS1 (pin 20). When
this pin is LOW, device is operated in software
mode by three-wire interface using ML (pin 1),
MD (pin 19) and MC (pin 20).
(1)
Digital Power Supply, +5V.
Digital Ground.
27MHz Crystal. When an external 27MHz clock
is applied to XT1 (pin 6), this pin must be
connected to GND.
27MHz Oscillator Input/External 27MHz Input.
Ground for PLL.
Power Supply for PLL, +5V.
Reserved. Must be left open.
27MHz Output.
Inverted 27MHz Output.
Fixed 33.8688MHz Clock Output.
768f
S
Clock Output.
256f
S
Clock Output.
Digital Ground for V
DDB
.
Digital Power Supply for Clock Output Buffers,
+3.3V.
384f
S
Output. This output has been optimized
for the lowest jitter and should be connected to
the audio DAC(s).
Reset. When this pin is LOW, device is held in
reset.
(1)
Serial Data Input for Software Mode/Sampling
Frequency Selection for Hardware Mode. When
MODE pin is LOW, MD is selected.
(1)
Shift Clock Input for Software Mode/Sampling
Frequency Selection for Hardware Mode. When
MODE pin is LOW, MC is selected.
(1)
ML/SR0
MODE
V
DD
GND
XT2
XT1
GNDP
V
DDP
RSV
1
2
3
4
5
PLL1700E
6
7
8
9
20
19
18
17
16
15
14
13
12
11
MC/FS1
2
MODE
IN
MD/FS0
RST
SCKO3
V
DDB
GNDB
SCKO2
SCKO4
SCKO1
MCKO
6
7
XT1
GNDP
V
DDP
RSV
MCKO
MCKO
SCKO1
SCKO4
SCKO2
GNDB
V
DDB
SCKO3
IN
—
—
—
OUT
OUT
OUT
OUT
OUT
—
—
OUT
3
4
5
V
DD
GND
XT2
—
—
—
MCKO 10
8
9
10
11
PACKAGE INFORMATION
TEMPERATURE
RANGE
–25°C to +85°C
PACKAGE
DRAWING
NUMBER
(1)
334-1
12
13
14
15
16
17
PRODUCT
PLL1700E
PACKAGE
20-Lead SSOP
NOTE: (1) For detailed drawing and dimension table, please see end of data
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