PLL1707
PLL1708
SLES065 – DECEMBER 2002
3.3 V DUAL PLL MULTICLOCK GENERATOR
FEATURES
D
27-MHz Master Clock Input
D
Generated Audio System Clock (PLL1707):
– SCKO0: 768 f
S
(f
S
= 44.1 kHz)
– SCKO1: 768 f
S
, 512 f
S
(f
S
= 48 kHz)
– SCKO2: 256 f
S
(f
S
= 32, 44.1, 48, 64, 88.2,
96 kHz)
– SCKO3: 384 f
S
(f
S
= 32, 44.1, 48, 64, 88.2,
96 kHz)
Generated Audio System Clock (PLL1708):
– SCKO0: 768 f
S
(f
S
= 44.1 kHz)
– SCKO1: 768 f
S
, 512 f
S
, 384 f
S
, 256 f
S
(f
S
= 48 kHz)
– SCKO2: 256 f
S
(f
S
= 16, 22.05, 24, 32, 44.1,
48, 64, 88.2, 96 kHz)
– SCKO3: 384 f
S
(f
S
= 16, 22.05, 24, 32, 44.1,
48, 64, 88.2, 96 kHz)
Zero PPM Error Output Clocks
Low Clock Jitter: 50 ps (Typical)
Multiple Sampling Frequencies (PLL1707):
– f
S
= 32, 44.1, 48, 64, 88.2, 96 kHz
Multiple Sampling Frequencies (PLL1708):
– f
S
= 16, 22.05, 24, 32, 44.1, 48, 64, 88.2,
96 kHz
3.3-V Single Power Supply
PLL1707: Parallel Control
PLL1708: Serial Control
Package: 20-Pin SSOP (150 mil), Lead-Free
Product
APPLICATIONS
D
D
D
D
D
D
D
HDD + DVD Recorders
DVD Recorders
HDD Recorders
DVD Players
DVD Add-On Cards for Multimedia PCs
Digital HDTV Systems
Set-Top Boxes
D
DESCRIPTION
The PLL1707
†
and PLL1708
†
are low cost, phase-locked
loop (PLL) multiclock generators. The PLL1707 and
PLL1708 can generate four system clocks from a 27-MHz
reference input frequency. The clock outputs of the
PLL1707 can be controlled by sampling frequency-control
pins and those of the PLL1708 can be controlled through
serial-mode control pins. The device gives customers both
cost and space savings by eliminating external
components and enables customers to achieve the very
low-jitter performance needed for high performance audio
DACs and/or ADCs. The PLL1707 and PLL1708 are ideal
for MPEG-2 applications which use a 27-MHz master
clock such as DVD recorders, HDD recorders, DVD
add-on cards for multimedia PCs, digital HDTV systems,
and set-top boxes.
D
D
D
D
D
D
D
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
†The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright
2002, Texas Instruments Incorporated
PLL1707
PLL1708
SLES065 – DECEMBER 2002
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
(MS)
SR
(MC)
FS2
(MD)
FS1
CSEL
VCC AGND VDD1–3 DGND1–3
Mode Control Interface
Reset
PLL2
XT1
OSC
XT2
PLL1
Power Supply
Divider
Divider
Divider
( ): PLL1708
MCKO1
MCKO2
SCKO0
SCKO1
SCKO2
SCKO3
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE CODE
OPERATION
TEMPERATURE
RANGE
–25°C to 85°C
25°C
–25°C to 85°C
25°C
PACKAGE
MARKING
PLL1707
PLL1708
ORDERING
NUMBER
PLL1707DBQ
PLL1707DBQ
PLL1708DBQ
SSOP 20
SSOP 20
20DBQ
20DBQ
PLL1707DBQR
PLL1708DBQ
PLL1708DBQR
TRANSPORT
MEDIA
Tube
Tape and reel
Tube
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PLL1705 AND PLL1706
Supply voltage: VCC, VDD1–VDD3
Supply voltage differences: VCC, VDD1–VDD3
Ground voltage differences: AGND, DGND1–DGND3
Digital input voltage: FS1 (MD), FS2 (MC), SR (MS), CSEL
Analog input voltage, XT1, XT2
Input current (any pins except supplies)
Ambient temperature under bias
Storage temperature
Junction temperature
Lead temperature (soldering)
4V
±0.1
V
±0.1
V
–
0.3 V to (VDD + 0.3) V
–
0.3 V to (VCC + 0.3) V
±10
mA
–40°C
to 125°C
–55°C to 150°C
150°C
260°C, 5 s
Package temperature (IR reflow, peak)
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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PLL1707
PLL1708
SLES065 – DECEMBER 2002
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25°C, VDD1–VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted)
PARAMETER
DIGITAL INPUT/OUTPUT
Logic input
VIH (1)
VIL (1)
IIH (1)
IIL (1)
VOH (2)
VOL (2)
Input logic level
Input logic current
Logic output
Output logic level
PLL1707
Sam ling
Sampling frequency
PLL1708
IOH = –4 mA
IOL = 4 mA
Standard fS
Double fS
Half fS
Standard fS
Double fS
VIN = VDD
VIN = 0 V
CMOS
VDD – 0.4 V
0.4
32
64
16
32
64
44.1
88.2
22.05
44.1
88.2
48
96
24
48
96
MHz
V
µA
Vp-p
ns
ns
55%
ps
1.5
ms
kHz
Vdc
Vdc
CMOS compatible
0.7VDD
65
3.6
0.3 VDD
100
±10
Vdc
µA
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MASTER CLOCK (MCKO1, MCKO2) CHARACTERISTICS
(fM = 27 MHz, C1 = C2 = 15 pF, CL = 20 pF on measurement pin)
Master clock frequency
26.73
27
27.27
VIH
VIL
IIH
IIL
Input level(3)
Input current(3)
Output voltage (4)
Output rise time
Output fall time
Duty cycle
Clock jitter (5)
Power-up time (6)
PLL AC CHARACTERISTICS (SCKO0–SCKO3)
(fM = 27 MHz, CL = 20 pF on measurement pin)
SCKO0
Fixed
SCKO1
SCKO2
SCKO3
SCKO0
SCKO1
SCKO2
SCKO3
Output rise time
Output fall time
Output duty cycle
Out ut
Output system clock
frequency
q
y
PLL1708
PLL1707
Selectable for 48 kHz
256 fS
384 fS
Fixed
Selectable for 48 kHz
256 fS
384 fS
20% to 80% of VDD
80% to 20% of VDD
45
12.288
4.096
6.144
24.576
8.192
12.288
12.288
18.432
33.8688
24.576
12.288
18.432
2.0
2.0
50
55
36.864
24.576
36.864
20% to 80% of VDD
80% to 20% of VDD
For crystal oscillation
For external clock
45%
VIN = VCC
VIN = 0 V
3.5
2.0
2.0
51%
50%
50
0.5
33.8688
36.864
24.576
36.864
0.7 VCC
0.3 VCC
±10
±10
MHz
ns
ns
%
(1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)
(2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1
(3) Pin 10: XT1
(4) Pin 11: XT2
(5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter
performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output.
(6) The delay time from power on to oscillation
(7) The settling time when the sampling frequency is changed
(8) The delay time from power on to lockup
(9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling
frequency selection and load condition.
(10) While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode.
3
PLL1707
PLL1708
SLES065 – DECEMBER 2002
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
all specifications at TA = 25°C, VDD1–VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted)
PARAMETER
Output clock jitter (5)
Frequency Settling Time(7)
Power-up time (8)
POWER SUPPLY REQUIREMENTS
VCC, VDD
IDD + ICC
Supply voltage range
Supply current (9)
Power dissipation
TEMPERATURE RANGE
Operating temperature
–25
85
°C
θ
JA
Thermal resistance
PLL1707/8DBQ: 20-pin SSOP (150 mil)
150
°C/W
(1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)
(2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1
(3) Pin 10: XT1
(4) Pin 11: XT2
(5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter
performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output.
(6) The delay time from power on to oscillation
(7) The settling time when the sampling frequency is changed
(8) The delay time from power on to lockup
(9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling
frequency selection and load condition.
(10) While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode.
VDD = VCC = 3.3 V, fS = 48 kHz
Power down(10)
VDD = VCC = 3.3 V, fS = 48 kHz
2.7
3.3
19
350
63
3.6
25
550
90
Vdc
mA
µA
mW
TEST CONDITIONS
SCKO0, SCKO1
SCKO2, SCKO3
PLL1707, to stated output frequency
PLL1708, to stated output frequency
To stated output frequency
MIN
TYP
58
50
50
80
3
MAX
100
100
150
300
6
UNIT
ps
ps
ns
ms
PIN ASSIGNMENTS
PLL1707
(TOP VIEW)
PLL1708
(TOP VIEW)
20
19
18
17
16
15
14
13
12
11
V
DD
1
SCKO2
SCKO3
DGND1
FS1
FS2
SR
V
CC
AGND
XT1
1
2
3
4
5
6
7
8
9
10
V
DD
3
SCKO1
SCKO0
DGND3
DGND2
MCKO2
MCKO1
V
DD
2
CSEL
XT2
V
DD
1
SCKO2
SCKO3
DGND1
MD
MC
MS
V
CC
AGND
XT1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
3
SCKO1
SCKO0
DGND3
DGND2
MCKO2
MCKO1
V
DD
2
CSEL
XT2
4
www.ti.com
PLL1707
PLL1708
SLES065 – DECEMBER 2002
PLL1707 Terminal Functions
TERMINAL
NAME
AGND
CSEL
DGND1
DGND2
DGND3
FS1
FS2
MCKO1
MCKO2
SCKO0
SCKO1
SCKO2
SCKO3
SR
VCC
VDD1
VDD2
VDD3
XT1
XT2
NO.
9
12
4
16
17
5
6
14
15
18
19
2
3
7
8
1
13
20
10
11
I/O
–
I
–
–
–
I
I
O
O
O
O
O
O
I
–
–
–
–
I
O
Analog ground
SCKO1 frequency selection control(1)
Digital ground 1
Digital ground 2
Digital ground 3
Sampling frequency group control 1(1)
Sampling frequency group control 2(1)
27-MHz master clock output 1
27-MHz master clock output 2
System clock output 0 (33.8688 MHz fixed)
System clock output 1 (selectable for 48 kHz)
System clock output 2 (256 fS selectable)
System clock output 3 (384 fS selectable)
Sampling rate control(1)
Analog power supply, 3.3 V
Digital power supply 1, 3.3 V
Digital power supply 2, 3.3 V
Digital power supply 3, 3.3 V
27-MHz crystal oscillator, or external clock input
27-MHz crystal oscillator, must be OPEN for external clock input mode
DESCRIPTION
(1) Schmitt-trigger input with internal pulldown.
5
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