V58C2256(804/164)SI
HIGH PERFORMANCE 256 Mbit DDR SDRAM
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4
DDR500
Clock Cycle Time (t
CK2
)
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK3
)
System Frequency (f
CK max
)
-
-
4ns
250 MHz
5
DDR400
7.5ns
6ns
5ns
200 MHz
6
DDR333
7.5ns
6ns
-
166 MHz
Features
-
-
-
-
-
-
Description
The V58C2256(804/164)SI is a four bank DDR
DRAM organized as 4 banks x 8Mbit x 8 (804) or 4 banks
x 4Mbit x 16 (164). The V58C2256(804/164)SI achieves
high speed data transfer rates by employing a chip ar-
chitecture that prefetches multiple bits and then syn-
chronizes the output data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock.
I/O transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A
sequential and gapless data rate is possible depending
on burst length, CAS latency and speed grade of the
device.
-
-
-
-
-
-
-
-
-
-
-
-
-
High speed data transfer rates with system
frequency up to 250 MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 66-pin 400 mil TSOP or 60 Ball FBGA
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
Differential clock inputs CK and CK
2.5V ± 0.2V Power Supply for DDR400/333
2.4V ~ 2.7V Power Supply for DDR500
tRAS lockout supported
Concurrent auto precharge option is supported
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
-40°C to 85°C
-40°C to 105°C
Package Outline
66-pin TSOP II
60 Ball FBGA
•
•
•
CK Cycle Time (ns)
-4
•
Power
Std.
•
•
•
-5
•
•
•
-6
•
•
•
L
•
•
•
Temperature
Mark
Blank
I
H
V58C2256(804/164)SI Rev.1.2 July 2011
1
编程基础
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
