V55C3256164VG
256Mbit SDRAM
(3.0~3.3) VOLT, TSOP II / FBGA PACKAGE
16M X 16
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
PRELIMINARY
7
143 MHz
7 ns
5.4 ns
6 ns
Features
■
4 banks x 4Mbit x 16 organization
■
High speed data transfer rates up to 166 MHz
■
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■
Single Pulsed RAS Interface
■
Data Mask for Read/Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency: 2, 3
■
Programmable Wrap Sequence: Sequential or
Interleave
■
Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■
Multiple Burst Read with Single Write Operation
■
Automatic and Controlled Precharge Command
■
Random Column Address every CLK (1-N Rule)
■
Deep Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval:
8192 cycles/64ms [0 to 70
o
C (Commercial)];
8192 cycles/64ms [-40 to 85
o
C (Industrial)];
8192 cycles/32ms [-40 to 105
o
C (H)];
8192 cycles/32ms [-40 to 125
o
C (Extended)]
■
Available in 54 Pin TSOP II, 54 Ball FBGA
■
LVTTL Interface
■
Single (+3.0~3.3) V
±0.3
V Power Supply
■
Drive Strength (DS) Option: Full, 1/2, 1/4 and 1/8
■
Auto Temperature Compensated Self Refresh
(Auto TCSR)
■
Operating Temperature Range:
Commercial (0
o
to 70
o
C)
Industrial (-40
o
to +85
o
C)
H (-40
o
to +105
o
C)
Extended (-40
o
to +125
o
C)
Description
The V55C3256164VG is a four bank Synchro-
nous DRAM organized as 4 banks x 4Mbit x 16. The
V55C3256164VG achieves high speed data trans-
fer rates up to 166 MHz by employing a chip archi-
tecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at
higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 166
MHz is possible depending on burst length, CAS
latency and speed grade of the device.
Device Usage Chart
Operating Temperature
Range
0°C to 70°C
-40
o
to 85
o
C
-40
o
to +105
o
C
-40
o
to +125
o
C
Package Outline
T/C
•
•
•
•
Access Time (ns)
6
•
•
•
•
Power
Std.
•
•
•
•
7PC
•
•
•
•
7
•
•
•
•
L
•
•
•
•
U
•
•
•
•
Temperature
Mark
Blank
I
H
E
V55C3256164VG Rev. 1.0 September 2008
1
ProMOS TECHNOLOGIES
Capacitance*
T
A
= 0 to 70°C, V
CC
= (3.0V~3.3) V
±
0.3 V, f = 1 MHz
Symbol Parameter
C
I1
C
I2
C
IO
C
CLK
Input Capacitance (A0 to A12)
Input Capacitance
RAS, CAS, WE, CS, CLK, CKE, DQM
Output Capacitance (I/O)
Input Capacitance (CLK)
V55C3256164VG
Absolute Maximum Ratings*
Max. Unit
5
5
pF
pF
6.5
4
pF
pF
Operating temperature range (commercial) 0 to 70°C
Operating temperature range (industrial)...-40 to 85°C
Operating temperature range (H)..............-40 to 105°C
Operating temperature range (extended) -40 to 125°C
Storage temperature range ............... -55 to 150 °C
Input/output voltage .................. -0.3 to (V
CC
+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ............................................. 1 W
Data out current (short circuit) ...................... 50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
*Note:Capacitance is sampled and not 100% tested.
Block Diagram
x16 Configuration
Column Addresses
A0 - A8, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
Column decoder
Sense amplifier & I(O) bus
8192 x 512
x 16 bit
8192 x 512
x16 bit
8192 x 512
x 16 bit
Column decoder
Sense amplifier & I(O) bus
8192 x 512
x 16 bit
Input buffer
Output buffer
Control logic & timing generator
I/O
1
-I/O
16
WE
LDQM
CAS
UDQM
CKE
RAS
CLK
CS
V55C3256164VG Rev1.0 September 2008
5
DSP 与 ARM 处理器
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