V54C3256(16/80)4VJ
256Mbit SDRAM, 3.3 VOLT
16M X 16, 32M X 8
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
166 MHz
6 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
Features
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-
-
-
-
-
-
-
-
-
Description
The V54C3256(16/80)4VJ is a four bank Syn-
chronous DRAM organized as 4 banks x 4Mbit x 16,
or 4 banks x 8Mbit x 8. The V54C3256(16/80)4VJ
achieves high speed data transfer rates up to 166
MHz by employing a chip architecture that prefetch-
es multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
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-
-
-
-
-
-
-
-
4 banks x 4Mbit x 16 organization
4 banks x 8Mbit x 8 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54 Pin TSOP II and 54 Ball FBGA
LVTTL Interface
Single +3.3 V ±0.3 V Power Supply
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
-25°C to 85°C
-40°C to 85°C
Package Outline
54 Pin TSOP II
54 Ball FBGA
•
•
•
6
•
•
•
Access Time (ns)
7
•
•
•
Power
Std.
•
•
•
Temperature
Mark
Blank
M
I
V54C3256(16/80)4VJ Rev. 1.4 July 2014
1
ProMOS TECHNOLOGIES
V54C3256(16/80)4VJ
Part Number Information
V
ProMOS
5 4
C
3
2 5 6 1 6
ORGANIZATION
& REFRESH
1Mx16, 2K : 1616
4Mx16, 4K : 6516
4
V
J
I
7
TYPE
54 : SDRAM
55 : MOBILE SDRAM
32Mx4, 4K : 12840
16Mx8, 4K : 12880
64Mx4, 8K : 25640
32Mx8, 8K : 25680
128Mx4, 8K : 51240
64Mx8, 8K : 51280
8Mx16, 4K : 12816
16Mx16, 8K : 25616
32Mx16, 8K : 51216
TEMPERATURE
BLANK: 0 - 70C
M : -25 - 85C
I:
H:
E:
-40 - 85C
-40 - 105C
-40 - 125C
CMOS
BANKS
VOLTAGE
2 : 2 BANKS
4 : 4 BANKS
8 : 8 BANKS
REV LEVEL
PACKAGE
LEAD
PLATING
SPECIAL FEATURE
L : LOW POWER GRADE
U : ULTRA LOW POWER GRADE
T
S
C
B
D
Z
R
E
F
G
H
RoHS
I/O
V: LVTTL
SPEED
7 : 143MHz
6 : 166MHz
4:
3:
2:
1:
3.0V
3.3 V
2.5 V
1.8 V
GREEN PACKAGE
DESCRIPTION
I
J
K
M
N
P
TSOP
60-Ball FBGA
54-BallFBGA
BGA
Die-stacked TSOP
Die-stacked FBGA
* RoHS: Restriction of Hazardous Substances
V54C3256(16/80)4VJ Rev. 1.4 July 2014
2
ProMOS TECHNOLOGIES
V54C3256(16/80)4VJ
Description
TSOP-II
Pkg.
I
Pin Count
54
54 Pin Plastic TSOP-II
x16 PIN CONFIGURATION
Top View
V
CC
I/O
1
V
CCQ
I/O
2
I/O
3
V
SSQ
I/O
4
I/O
5
V
CCQ
I/O
6
I/O
7
V
SSQ
I/O
8
V
CC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356164V-01
Pin Names
CLK
CKE
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.0V~3.3V)
Ground
Power for I/O’s (+3.0V~3.3V)
Ground for I/O’s
Not connected
V
SS
I/O
16
V
SSQ
I/O
15
I/O
14
V
CCQ
I/O
13
I/O
12
V
SSQ
I/O
11
I/O
10
V
CCQ
I/O
9
V
SS
NC
UDQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
CS
RAS
CAS
WE
A
0
–A
12
BA0, BA1
I/O
1
–I/O
16
LDQM, UDQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V54C3256(16/80)4VJ Rev. 1.4 July 2014
3
ProMOS TECHNOLOGIES
V54C3256(16/80)4VJ
Description
TSOP-II
Pkg.
I
Pin Count
54
54 Pin Plastic TSOP-II
x8 PIN CONFIGURATION
Top View
Pin Names
CLK
CKE
CS
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.0V~3.3V)
Ground
Power for I/O’s (+3.0V~3.3V)
Ground for I/O’s
Not connected
V
CC
I/O
1
V
CCQ
NC
I/O
2
V
SSQ
NC
I/O
3
V
CCQ
NC
I/O
4
V
SSQ
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356804V-01
V
SS
I/O
8
V
SSQ
NC
I/O
7
V
CCQ
NC
I/O
6
V
SSQ
NC
I/O
5
V
CCQ
NC
V
SS
NC
DQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
RAS
CAS
WE
A
0
–A
12
BA0, BA1
I/O
1
–I/O
8
DQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V54C3256(16/80)4VJ Rev. 1.4 July 2014
4
ProMOS TECHNOLOGIES
V54C3256(16/80)4VJ
Description
FBGA
Pkg.
K
Pin Count
54
54 BALL FBGA
x16 PIN CONFIGURATION
Top View
n for x16 devic es :
Pin Names
CLK
CKE
CS
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.0V~3.3V)
Ground
Power for I/O’s (+3.0V~3.3V)
Ground for I/O’s
Not connected
1
2
3
A
B
C
D
E
F
G
H
J
7
8
9
V DD
DQ1
DQ3
DQ5
RAS
CAS
WE
A
0
–A
12
BA0, BA1
DQ
0
–DQ
15
LDQM, UDQM
V S S DQ15 V S S Q
DQ14 DQ13 V DDQ
DQ12 DQ11 V S S Q
DQ10 DQ9 V DDQ
DQ8
NC
VS S
CKE
A9
A6
A4
V DDQ DQ0
V S S Q DQ2
V DDQ DQ4
V S S Q DQ6
V DD LDQM DQ7
C AS
B A0
A0
A3
R AS
B A1
A1
A2
WE
CS
A10
V DD
UDQM C LK
A 12
A8
VS S
A11
A7
A5
V
CC
V
SS
V
CCQ
V
SSQ
NC
< Top-view >
V54C3256(16/80)4VJ Rev. 1.4 July 2014
5
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