PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
FEATURES
•
•
•
•
•
•
•
•
•
•
VCXO output for the 17MHz to 36MHz range
Low phase noise (-130 dBc @ 10kHz offset at
35.328MHz).
CMOS output with OE tri-state control.
17 to 36MHz fundamental crystal input.
Integrated high linearity variable capacitors.
12mA drive capability at TTL output.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5 to 3.3V operation.
Available in 8-Pin SOIC, 6-pin SOT23 packages,
or DIE.
BLOCK DIAGRAM
PIN CONFIGURATION
XIN
VDD*
VIN
GND
1
2
3
4
8
7
6
5
XOUT
OE^
VDD*
CLK
^: Denotes internal Pull-up
*: Only one VDD pin needs to be connected
PLL500-17
DESCRIPTION
The PLL500-17 is a low cost, high performance and
low phase noise VCXO for the 17 to 36MHz range,
providing less than -130dBc at 10kHz offset at
35.328MHz. The very low jitter (2.5 ps RMS period
jitter) makes this chip ideal for applications requiring
voltage controlled frequency sources. Input crystal
can range from 17 to 36MHz (fundamental resonant
mode).
OUT
GND
CLK
1
2
3
6
5
4
XIN
VDD
VIN
PLL500-17
FREQUENCY RANGE
MULTIPLIER
No PLL
FREQUENCY
17 – 36 MHz
OUTPUT
BUFFER
CMOS
8-pin SOIC
6-pin SOT
XIN
XOUT
XTAL
OSC
VARICAP
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 03/29/05 Page 1
PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
DIE PAD LAYOUT
32 mil
(812,986)
DIE SPECIFICATIONS
Name
Value
8
1
XIN
XOUT
OE^ 7
39 mil
2
VDD
VDD 6
Size
Reverse side
Pad dimensions
Thickness
39 x 32 mil
GND
80 micron x 80 micron
10 mil
3 VCON
4 GND
CLK 5
DIE ID:
PLL500-17: C500A0404-04A
Y
X
(0,0)
Note: ^ denotes internal pull up
PIN ASSIGNMENT (8-pin SOIC package) AND PAD DESCRIPTION (8-pin SOIC pack-
age)
Name
XIN
VDD
VCON
GND
CLK
VDD
OE
XOUT
Pin#
1
2
3
4
5
6
7
8
Die Pad Position
X (µm)
94.183
94.157
94.183
94.193
715.472
715.307
715.472
476.906
Y (µm)
768.599
605.029
331.756
140.379
203.866
455.726
626.716
888.881
Type
I
P
I
P
O
P
I
I
Description
Crystal input pin.
VDD power supply pin. Only one VDD pin is necessary.
Frequency control voltage input pin.
Ground pin.
Output clock pin.
VDD power supply pin. Only one VDD pin is necessary.
Output Enable input pin. Disables the output when low. Internal
pull-up enables output by default if pin is not connected to low.
Crystal output pin. Ref Clock input.
* OE (Output Enable) pin is not available in SOT-26 package, the output will always be enabled by the build in pull-up resister.
PIN ASSIGNMNET AND DESCRIPTION (6-pin SOIC package)
Name
XOUT
GND
CLK
VCON
VDD
XIN
Pin#
1
2
3
4
5
6
Type
I
P
O
I
P
I
Description
Crystal Output pin. Ref. Clock input.
Ground pin.
Output clock pin.
Frequency control voltage input pin.
VDD power supply pin.
Crystal input pin.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 03/29/05 Page 2
PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Short Circuit Current
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Measured @ 1.4V
45
SYMBOL
CONDITIONS
MIN.
17
TYP.
1.15
3.7
50
±50
MAX.
36
UNITS
MHz
ns
55
%
mA
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
Power Supply Rejection
VCON pin input impedance
VCON modulation BW
PWSRR
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 12 – 25MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
VCON=1.65V,
±1.65V
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
ppm/V
%
ppm
kΩ
kHz
300
±150
100
5
Frequency change with
VDD varied +/- 10%
0V
≤
VCON
≤
3.3V, -3dB
-1
2000
45
+1
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. Jitter and Phase Noise Specifications
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 03/29/05 Page 3
PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
PARAMETERS
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
CONDITIONS
With capacitive decoupling between
VDD and GND.
36MHz @100Hz offset
36MHz @1kHz offset
36MHz @10kHz offset
36MHz @100kHz offset
36MHz @1MHz offset
MIN.
TYP.
2.5
-80
-110
-130
-138
-145
MAX.
UNITS
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
5. DC Specifications
PARAMETERS
Supply Current, Dynamic,
with Loaded Outputs
Operating Voltage
Output Low Voltage at
CMOS level
Output High Voltage at
CMOS level
Output drive current
Short Circuit Current
VCXO Control Voltage
SYMBOL
I
DD
V
DD
V
OLC
V
OHC
CONDITIONS
F
XIN
= 36MHz
Output load of 15pF
MIN.
TYP.
5
MAX.
6
3.63
0.4
UNITS
mA
V
V
V
2.25
I
OL
= +4mA
I
OH
= -4mA
For V
OL
<0.4V or V
OH
>2.4V
V
DD
– 0.4
8
0
9.5
±50
VCON
V
DD
mA
mA
V
6. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating (VCON = 1.65V)
Maximum Sustainable Drive Level
Operating Drive Level
C0
C0/C1
ESR
SYMBOL
F
XIN
C
L (xtal)
MIN.
17
TYP.
8.5
MAX.
36
200
UNITS
MHz
pF
µW
µW
pF
-
Ω
50
5
250
30
R
S
Note:
The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 03/29/05 Page 4
PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
PACKAGE INFORMATION
8 PIN ( dimensions in mm )
Narrow SOIC
Symbol
A
A1
B
C
D
E
H
L
e
Min.
1.47
0.10
0.33
0.19
4.80
3.80
5.80
0.38
Max.
1.73
0.25
0.51
0.25
4.95
4.00
6.20
1.27
1.27 BSC
A
1
e
B
A
C
L
D
E
H
6-pin SOT (Dimensions in mm)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 03/29/05 Page 5
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