PLL500-27/-37/-47
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
FEATURES
•
VCXO output for the 27MHz to 200MHz range
-
PLL500-27: 27MHz to 65MHz
-
PLL500-37: 65MHz to 130MHz
-
PLL500-47: 100MHz to 200MHz
Low phase noise (-130 dBc @ 10kHz offset).
CMOS output with OE tri-state control.
Selectable output drive (Standard or High drive).
-
Standard: 12mA drive capability at TTL level.
-
High: 36mA drive capability at TTL level.
Fundamental crystal input.
Integrated high linearity variable capacitors.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5-3.3V operation.
Available in 8-Pin SOIC or DIE.
PIN CONFIGURATION
XIN
DRIVSEL^
VCON
GND
1
2
3
4
8
7
6
5
XOUT
OE^
VDD
CLK
PLL500-x7
•
•
•
•
•
•
•
•
•
^: Denotes internal Pull-up
DIE PAD LAYOUT
8
1
2
7
6
3
4
5
DESCRIPTION
The PLL500-27/-37/-47 are a low cost, high perform-
ance, low phase noise, and high linearity VCXO fam-
ily for the 27 to 200MHz range, providing less than -
130dBc at 10kHz offset. The very low jitter (2.5 ps
RMS period jitter) makes these chips ideal for appli-
cations requiring voltage controlled frequency
sources. The IC’s are designed to accept fundamen-
tal resonant mode crystals.
FREQUENCY RANGE
PART #
PLL500-27
PLL500-37
PLL500-47
MULTIPLIER
No PLL
No PLL
No PLL
FREQUENCY
27 – 65 MHz
65 – 130 MHz
100 – 200 MHz
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
VARICAP
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/21/04 Page 1
PLL500-27/-37/-47
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
PIN AND PAD DESCRIPTION
Name
XIN
DRIVSEL
VCON
GND
CLK
VDD
OE
XOUT
Pin#
1
2
3
4
5
6
7
8
Die Pad Position
X (µ m)
µ
94.183
94.157
94.183
94.193
715.472
715.307
715.472
476.906
Y (µ m)
µ
768.599
605.029
331.756
140.379
203.866
455.726
626.716
888.881
Type
I
I
I
P
O
P
I
I
Crystal input pin.
Description
Output drive select pin. High drive if set to ‘0’. Low drive if set
to ‘1’. Internal pull-up.
Frequency control voltage input pin.
Ground pin.
Output clock pin.
VDD power supply pin.
Output Enable input pin. Disables the output when low. Internal
pull-up enables output by default if pin is not connected low.
Crystal output pin. Ref clock input.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature
Storage Temperature
Ambient Operating Temperature
T
S
-65
0
SYMBOL
V
CC
V
I
V
O
MIN.
MAX.
7
V
CC
+
0.5
V
CC
+
0.5
260
150
70
UNITS
V
V
V
°C
°C
°C
-
0.5
-
0.5
-
0.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/21/04 Page 2
PLL500-27/-37/-47
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
2. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
SYMBOL
CONDITIONS
PLL500-27
PLL500-37
PLL500-47
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Measured @ 1.4V
MIN.
27
65
100
TYP.
MAX.
65
130
200
UNITS
MHz
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Short Circuit Current
1.15
3.7
45
50
±50
55
ns
%
mA
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
Power Supply Rejection
VCON pin input impedance
VCON modulation BW
0V
≤
VCON
≤
3.3V, -3dB
PWSRR
Frequency change with
VDD varied +/- 10%
-1
1000
45
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
MIN.
TYP.
10
MAX.
UNITS
ms
ppm
ppm
300
±150
100
5
+1
ppm/V
%
ppm
kΩ
kHz
Note:
Preliminary Specifications still to be characterized. Parameters denoted with an asterisk (*) represent nominal characterization data and are not
production tested to any specific limits.
4. Jitter and Phase Noise specification
PARAMETERS
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
CONDITIONS
With capacitive decoupling
between VDD and GND.
@100Hz offset
@1kHz offset
@10kHz offset
@100kHz offset
@1MHz offset
MIN.
TYP.
2.5
-80
-110
-130
-138
-145
MAX.
UNITS
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/21/04 Page 3
PLL500-27/-37/-47
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
5. DC Specification
PARAMETERS
Supply Current, Dynamic,
with Loaded Outputs
SYMBOL
I
DD
CONDITIONS
F
XIN
= 36MHz, 15pF output load
F
XIN
= 77MHz, 15pF output load
F
XIN
= 155MHz, 15pF output load
PLL500-27
MIN.
TYP.
5
10
15
MAX.
6
12
18
N/A
15
10
UNITS
mA
pF
pF
pF
V
V
V
V
Allowable output load
capacitance
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage at
CMOS level
Output drive current
Short Circuit Current
VCXO Control Voltage
ESD Protection
C
L
(Output)
V
DD
V
OH
V
OL
PLL500-37 and-47: Std drive
PLL500-37 and-47: High drive
2.25
I
OH
= -12mA
I
OL
= 12mA
I
OH
= -4mA
Standard drive at TTL level
High drive at TTL level
V
DD
– 0.4
12
36
17
51
±50
2.4
3.63
0.4
mA
mA
3.3
V
V
VCON
Human Body Model
0
2000
6. Crystal Specifications
PARAMETERS
Crystal Loading Rating (VCON = 1.65V)
Maximum Sustainable Drive Level
Operating Drive Level
Max C0 for PLL500-27
Max C0 for PLL500-37
Max C0 for PLL500-47
C0/C1
ESR
R
S
50
3.5
2.5
2
250
30
-
Ω
pF
SYMBOL
C
L
(xtal)
MIN.
TYP.
8.5
MAX.
UNITS
pF
200
µW
µW
Note:
The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/21/04 Page 4
PLL500-27/-37/-47
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
PACKAGE INFORMATION
8 PIN ( dimensions in mm )
Narrow SOIC
Symbol
A
A1
B
C
D
E
H
L
e
Min.
1.47
0.10
0.33
0.19
4.80
3.80
5.80
0.38
Max.
1.73
0.25
0.51
0.25
4.95
4.00
6.20
1.27
1.27 BSC
B
e
A
1
C
L
A
D
E
H
ORDERING INFORMATION
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PART NUMBER
PLL500-x7 x x
Part Number
Temperature
C=Commercial
Package
S=SOIC
D=Die
Order Number
PLL500-27SC
PLL500-27SC-R
PLL500-27DC
PLL500-37SC
PLL500-37SC-R
PLL500-37DC
PLL500-47SC
PLL500-47SC-R
PLL500-47DC
Marking
P500-27SC
P500-27SC
P500-27DC
P500-37SC
P500-37SC
P500-37DC
P500-47SC
P500-47SC
P500-47DC
Package Option
8-Pin SOIC (Tube)
8-Pin SOIC (Tape and Reel)
Die (Waffle Pack)
8-Pin SOIC (Tube)
8-Pin SOIC (Tape and Reel)
Die (Waffle Pack)
8-Pin SOIC (Tube)
8-Pin SOIC (Tape and Reel)
Die (Waffle Pack)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/21/04 Page 5
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
