Locked Loop techniques to allow the user to select
the desired multiplier value. The chip accepts crystal
or clock inputs ranging from 10 to 30MHz, depening
on selected multiplier, and produces outputs clocks
up to 198MHz at 3.3V.
MULTIPLIER SELECT TABLE
S3
0
0
1
1
S2
0
0
1
0
1
S1
0
0
0
0
0
S0
0
1
1
1
1
Multiplier
Xtal range
0
Reserved
11x
10–18MHz
5x
20-30MHz
Frequency Pass through
6x
11-22MHz
BLOCK DIAGRAM
S3
S2
S1
S0
ROM Based
Multipliers
Phase
Locked
Loop
OE
CLK
XIN
XOUT
XTAL
OSC
REFOUT
REFEN
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 06/15/01 Page 1
Preliminary
PLL601-03
Low Phase Noise PLL Clock Multiplier
PIN DESCRIPTIONS
Name
CLK
REFEN
VDD
XIN
XOUT
OE
REFOUT
S0
S1
S2
S3
GND
Number
1
2
3,4,5
8
6
12
13
11
7
9
10
14,15,16
Type
O
I
P
I
O
I
O
I
I
I
I
P
Description
Clock output from VCO. Equals the input frequency times multiplier.
Reference clock enable. When Low, it turns off REFOUT.
3.3V Power Supply.
Crystal input to be connected to 10-30MHz fundamental parallel mode crys-
tal (C
L
=15pF). On chip load capacitors: No external capacitor required.
Crystal Connection.
Output Enable. Tri-state CLK and REFOUT when low. Has internal pull-up.
Buffered crystal oscillator clock output. Controlled by REFEN.
Multiplier Select Pin 0. Determines CLK output. Has internal pull-up.
Multiplier Select Pin 1. Determines CLK output. Has internal pull-up.
Multiplier Select Pin 1. Determines CLK output. Has internal pull-up.
Multiplier Select Pin 3. Determines CLK output. Has internal pull-up.
Ground.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 06/15/01 Page 2
Preliminary
PLL601-03
Low Phase Noise PLL Clock Multiplier
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature
Storage Temperature
Ambient Operating Temperature
T
S
-65
0
SYMBOL
V
CC
V
I
V
O
MIN.
MAX.
7
V
CC
+
0.5
V
CC
+
0.5
260
150
70
UNITS
V
V
V
°C
°C
°C
-
0.5
-
0.5
-
0.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
2. AC Specification
PARAMETERS
Input Frequency
Output Frequency
Output Rise Time
Output Fall Time
Duty Cycle
Period jitter RMS
Accumulated jitter RMS
Phase Noise, relative to carrier, 155Mhz(x8)
Phase Noise, relative to carrier, 155Mhz(x8)
Phase Noise, relative to carrier, 155Mhz(x8)
Phase Noise, relative to carrier, 155Mhz(x8)
At 3.3V
0.8V to 2.0V with no load
2.0V to 0.8V with no load
At VDD/2
With capacitive decoupling
between VDD and GND
With capacitive decoupling
between VDD and GND
100Hz offset, 3.3V
1kHz offset, 3.3V
10kHz offset, 3.3V
100kHz offset, 3.3V
45
50
6.4
9.4
-103
-126
-133
-128
CONDITIONS
Depends on selected multiplier
MIN.
10
TYP.
MAX.
30
160
1.5
1.5
55
UNITS
MHz
MHz
ns
ns
%
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 06/15/01 Page 3
Preliminary
PLL601-03
Low Phase Noise PLL Clock Multiplier
3. DC Specification
PARAMETERS
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage At
CMOS Level
Operating Supply Current
Short-circuit Current
Input Capacitance
SYMBOL
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
I
DD
I
S
C
IN
CONDITIONS
MIN.
3.135
2
TYP.
MAX.
3.465
0.8
UNITS
V
V
V
V
V
V
V
V
For XIN pin
For XIN pin
I
OH
= -25mA
I
OL
= 25mA
I
OH
= -8mA
No Load
OE, Select Pins
(VDD/2)
+
1
2.4
VDD/2
VDD/2
(VDD/2)
−
1
0.4
VDD-0.4
35
±120
5
mA
mA
pF
4. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Capacitance
Rating
SYMBOL
F
XIN
C
L
(xtal)
CONDITIONS
Parallel Fundamental Mode
MIN.
10
TYP.
MAX.
30
UNITS
MHz
pF
15
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 06/15/01 Page 4
Preliminary
PLL601-03
Low Phase Noise PLL Clock Multiplier
PACKAGE INFORMATION
16 PIN Narrow SOIC, TSSOP ( mm )
SOIC
Symbol
A
A1
B
C
D
E
H
L
e
Min.
1.35
0.10
0.33
0.19
9.80
3.80
5.80
0.40
1.27 BSC
Max.
1.75
0.25
0.51
0.25
10.00
4.00
6.20
1.27
0.45
Min.
-
0.05
0.19
0.09
4.90
4.30
TSSOP
Max.
1.20
0.15
0.30
0.20
5.10
4.50
6.40 BSC
0.75
0.65 BSC
B
e
A1
A
C
L
D
E
H
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PART NUMBER
PLL601-03 X C
PART NUMBER
TEMPERATURATURE
C=COMMERCIAL
M=MILITARY
I=INDUSTRAL
PACKAGE TYPE
S=SOIC, O=TSSOP
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
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