chips. They provide phase noise performance as low
as –125dBc at 1kHz offset (at 155MHz) and a typical
RMS jitter of 4pS RMS ( at 155MHz ). They accept
fundamental parallel resonant mode crystals from 12
to 25MHz.
VDD / GND*
DESCRIPTION
XIN
SEL0^ / VDD*
10
XOUT
SEL3^
SEL2^
OE
13
14
15
16
12
11
SEL1^
9
8
7
6
5
GND
CLKC
VDD
CLKT
PLL602-3X
1
2
3
4
GND
GND
SEL
OE
PLL
(Phase
Locked
Loop)
^:
*:
Q
Q
Internal pull-up
On 3x3 package, PLL602-35/-38 do not have SEL0 available: Pin
10 is VDD, pin 11 is GND. However, PLL602-37/-39 have SEL0
(pin 10), and pin 11 is VDD. See pin assignment table for details.
XIN
XOUT
Oscillator
Amplifier
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL602-3x
PLL by-pass
PLL602-38
PLL602-35
PLL602-37
PLL602-39
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by PECL levels for PLL602-38
Logical states defined by CMOS levels for
PLL602-35/-37/-39
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 1
GND
GND
BLOCK DIAGRAM
PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
FREQUENCY SELECTION TABLE
SEL3
SEL2
SEL1
SEL0
Selected Multiplier
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
0
1
1
0
1
0
1
0
1
Fin x 32
Fin / 8
Fin x 2
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
Note:
SEL0 is not available (always “1”) for PLL602-35 and PLL602-38 in 3x3mm package
PIN DESCRIPTIONS PLL602-35 and PLL602-38 (see next page of PLL602-37/-39)
Name
XIN
XOUT
OE
GND
CLKT
CLKC
SEL0
SEL1
SEL2
SEL3
VDD
TSSOP
Pin number
2
3
6
7,8,9,10,14
11
13
16
15
5
4
1, 12
3x3mm QFN
Pin number
12
13
16
1,2,3,4,8,11
5
7
Not available
9
15
14
6,10
Type
I
I
I
P
O
O
I
I
I
I
P
Description
Crystal input. See Crystal Specifications on page 3.
Crystal output. See Crystal Specifications on page 3.
Output enable pin (see OE logic state table on page 1).
Ground.
True output PECL
Complementary output PECL.
Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND.
Power Supply.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 2
PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
PIN DESCRIPTIONS PLL602-37/-39 (see previous page of PLL602-35/-38)
Name
XIN
XOUT
OE
GND
CLKT
CLKC
SEL0
SEL1
SEL2
SEL3
VDD
TSSOP
Pin number
2
3
6
7,8,9,10,14
11
13
16
15
5
4
1, 12
3x3mm QFN
Pin number
12
13
16
1,2,3,4,8
5
7
10
9
15
14
6,11
Type
I
I
I
P
O
O
I
I
I
I
P
Description
Crystal input. See Crystal Specifications on page 3.
Crystal output. See Crystal Specifications on page 3.
Output enable pin (see OE logic state table on page 1).
Ground.
True output LVDS (PLL602-39)
(N/C for PLL602-37)
Complementary output LVDS (PLL602-39)
(CMOS out for PLL602-37).
Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND.
Power Supply.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
R
E
CONDITIONS
Parallel Fundamental Mode
AT cut
MIN.
12
TYP.
20
MAX.
25
30
UNITS
MHz
pF
Ω
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 3
PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
3. General Electrical Specifications
PARAMETERS
Supply Current,
Dynamic (with
Loaded Outputs)
Operating Voltage
Output Clock
Duty Cycle
Short Circuit
Current
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS/CMOS
Fout<24MHz
24MHz<Fout<96MHz
96MHz<Fout<800MHz
MIN.
TYP.
MAX.
25/25/15
65/45/30
100/80/40
3.63
55
55
55
UNITS
mA
V
%
mA
2.97
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@
V
DD
– 1.3V (PECL)
45
45
45
50
50
50
±50
4. Jitter Specifications
PARAMETERS
CONDITIONS
With capacitive decoupling be-
tween VDD and GND.
Over 10,000 cycles.
FREQUENCY
19.44MHz
77.76MHz
155.52MHz
622.08MHz
19.44MHz
77.76MHz
155.52MHz
622.08MHz
155.52MHz
622.08MHz
MIN.
TYP.
2.2
3.5
4.3
5.0
17
25
27
35
2.6
2.5
MAX.
UNITS
Period jitter
RMS
1
ps
Period jitter Peak-to-
Peak
1
With capacitive decoupling be-
tween VDD and GND.
Over 10,000 cycles.
Integrated 12 kHz to 20 MHz
ps
Integrated jitter RMS
2
4
4
ps
5. Phase Noise Specifications
PARAMETERS
Phase
to carrier
(typical)
Noise
2
relative
FREQUENCY
19.44MHz
77.76MHz
155.52MHz
622.08MHz
@10Hz
-80
-72
-65
-55
@100Hz
-108
-103
-95
-85
@1kHz
-132
-122
-120
-109
@10kHz
-142
-130
-125
-115
@100kHz
-150
-125
-121
-110
UNITS
dBc/Hz
6. CMOS Electrical Characteristics
PARAMETERS
Output drive current
Output Clock Rise/Fall Time
SYMBOL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
MIN.
10
10
TYP.
MAX.
UNITS
mA
mA
ns
2.4
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 4
PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
7. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
0.9
1.125
0
V
out
= V
DD
or GND
V
DD
= 0V
8. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50Ω
C
L
= 10pF
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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