resistor *: Bi-directional pin (input value is latched upon power-up).
DESCRIPTION
The PLL650-05 is a low cost, low jitter, high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, this
device can produce multiple clock outputs from a 25.0MHz
crystal or reference clock. This makes the PLL650-05 an
excellent choice for systems requiring clocking for network
chips, PCI devices, SDRAM, and ASICs.
FREQUENCY TABLE
FS1
0
0
1
1
FS0
0
1
0
1
SDRAMX2
Tristate
140MHz
SST
83.3MHz
SST
105MHz
SST
BLOCK DIAGRAM
1
XIN
XOUT
XTAL
OSC
125MHz
(can be disabled)
1
Control
Logic
FS (0:1)
SDRAM (105, 83.3, 140MHz)
75 MHz
(can be disabled)
1
1
25MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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Rev 09/03/04 Page 1
PLL650-05
Low EMI Network LAN Clock
PIN DESCRIPTIONS
Name
XIN
XOUT/ENB_125M
125MHz
75MHz/FS1
ENB_75M
SS0
SDRAMx2
25MHz/FS0
VDD
GND
Number
1
2
5
7
8
9
11
14
4,10,15,16
3,6,12,13
Type
I
B
O
B
I
I
O
B
P
P
Description
25MHz fundamental crystal input (20pF C
L
parallel resonant).
Crystal output. At power-up, this pin latches ENB_125M (output enable
selector for 125MHz output. Disabled when ENB_125M is logical zero. Has
120kΩ internal pull up resistor.
125MHz output.
75MHz output. This pin latch FS1 value at power-up. It has 60kΩ internal
pull up resistors.
Output enable for 75Mhz output when high. Disabled when ENB_75M is
logical low. It has 60KΩ internal pull up resistor.
This pin is a tri-level input pin to control the spread spectrum function. See
Spread Spectrum Selection Table
SDRAM outputs with double drive strength determined by FS(0:1) value.
25MHz (reference) output. This pin latch FS0 value at power-up. It has 60kΩ
internal pull up resistors.
Power supply.
Ground.
SPREAD SPECTRUM SELECTION TABLE
SS0
0
M
1
SST
±0.75%
Center
OFF
±0.5%
Center
FUNCTIONAL DESCRIPTION
Selectable spread spectrum and output frequencies
The PLL650-05 provides selectable spread spectrum modulation and selectable output frequencies. Selection is made by
connecting specific pins to a logical “zero” or “one”, or by leaving them not connected (tri-level inputs or internal pull-up)
according to the frequency and spread spectrum selection tables shown on pages 1 and 2 respectively.
In order to reduce pin usage, the PLL650-05 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0
(Connect to GND), 1 (Connect to VDD), M (Do not connect). Thus, unlike the two-level selection pins, the tri-level input pins are
in the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to
GND. Likewise, in order to connect to a logical “one” the pin must be connected to VDD.
Connecting a bi-directional pin
A bi-directional pin serves as input upon power-up, and as output as soon as the inputs have been latched. The value of the
input is latched-in upon power-up. Depending on the pin (see pin description), the input can be tri-level or a standard two-level.
Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in order to set the input to "0" or "1",
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 2
PLL650-05
Low EMI Network LAN Clock
since the pin also needs to serve as output. In the case of two level input pins, an internal pull-up resistor is present. This allows
a default value to be set when no external pull down resistor is connected between the pin and GND (by definition, a tri-level
input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-directional pin to a non-default value, the
input must be connected to GND or VDD through an external pull-down/pull-up resistor.
Note:
when the output load presents a
low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor may not be sufficient to pull the input up
to a logical “one”, and an external pull-up resistor may be required.
For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the
internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the
pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is
recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application
Diagram).
Note:
when the output is used to drive a load presenting an small resistance between the output pin and VDD, this
resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may
have to be dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical “zero”. This is
particularly true when driving 74FXX TTL components.
APPLICATION DIAGRAM
Internal to chip
VDD
External Circuitry
R
up
Power Up
Reset
R
RB
Output
EN
Bi-directional pin
Clock Load
Latched
Input
Latch
R
UP
/
4
Jumper options
NOTE:
Rup=120kΩ for 50MHz_OE (Pin2); Rup=60k
Ω
for FS(0:1). R starts from 1 to 0 while RB starts from 0 to 1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 3
PLL650-05
Low EMI Network LAN Clock
Electrical Specifications
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Specifications
PARAMETERS
Input Frequency
Output Rise Time
Output Fall Time
Duty Cycle*
Max. Absolute Jitter
Max. Jitter, cycle to cycle
CONDITIONS
0.8V to 2.0V with no load
2.0V to 0.8V with no load
@ 50% V
DD
Short term
MIN.
10
TYP.
25
MAX.
27
1.5
1.5
55
80
UNITS
MHz
ns
ns
%
ps
ps
45
50
±150
* : in case SDRAM output is selected to be 83.3MHz, the duty cycle of output pin 22 will be 40%-60% if its output frequency is selected to be 105MHz
(FS2=1). In all other situations, pin 22 will also have a 50%-50% typical duty cycle.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 4
PLL650-05
Low EMI Network LAN Clock
3. DC Specification
PARAMETERS
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage At
CMOS Level
Operating Supply Current
Short-circuit Current
Nominal output current*
Nominal output current*
Internal pull-up resistor
Internal pull-up resistor
SYMBOL
V
DD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
I
DD
I
S
I
out
I
out
R
up
R
up
CONDITIONS
MIN.
2.97
TYP.
V
DD
/2
V
DD
/2
MAX.
3.63
V
DD
/2 - 1
0.5
UNITS
V
V
V
V
V
V
V
V
V
V
For all Tri-level input
For all Tri-level input
For all normal input
For all normal input
I
OH
= -25mA
I
OL
= 25mA
I
OH
= -8mA
No Load
CMOS output level
TTL output level
Pins 5,7
Pin 2
V
DD
-0.5
2
0.8
2.4
0.4
V
DD
-0.4
35
35
20
±50
40
25
60
120
mA
mA
mA
mA
kΩ
kΩ
*: SDRAM output strengths are doubled (i.e. min. CMOS level is 70mA, typ. CMOS level is 80mA)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
FPGA/CPLD
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