Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16
×
48
×
8)
PLS100/PLS101
DESCRIPTION
The PLS100 (3-State) and PLS101 (Open
Collector) are bipolar, fuse Programmable
Logic Arrays (PLAs). Each device utilizes the
standard AND/OR/Invert architecture to
directly implement custom sum of product
equations.
Each device consists of 16 dedicated inputs
and 8 dedicated outputs. Each output is
capable of being actively controlled by any or
all of the 48 product terms. The True,
Complement, or Don’t Care condition of each
of the 16 inputs and be ANDed together to
comprise one P-term. All 48 P-terms can be
selectively ORed to each output.
The PLS100 and PLS101 are fully TTL
compatible, and chip enable control for
expansion of input variables and output
inhibit. They feature either Open Collector or
3-State outputs for ease of expansion of
product terms and application in
bus-organized systems.
Order codes are listed in the Ordering
Information Table.
FEATURES
•
Field-programmable (Ni-Cr link)
•
Input variables: 16
•
Output functions: 8
•
Product terms: 48
•
I/O propagation delay: 50ns (max.)
•
Power dissipation: 600mW (typ.)
•
Input loading: –100µA (max.)
•
Chip Enable input
•
Output option:
–
PLS100: 3-State
–
PLS101: Open-Collector
PIN CONFIGURATIONS
N Package
FE
*
1
I7 2
I6 3
I5 4
I4 5
I3 6
I2 7
I1 8
I0 9
F7 10
F6 11
F5 12
F4 13
GND 14
28 V
CC
27 I8
26 I9
25 I10
24 I11
23 I12
22 I13
21 I14
20 I15
19 CE
18 F0
17 F1
16 F2
15 F3
•
Output disable function:
–
3-State: Hi-Z
–
Open-Collector: High
*
APPLICATIONS
•
CRT display systems
•
Code conversion
•
Peripheral controllers
•
Function generators
•
Look-up and decision tables
•
Microprogramming
•
Address mapping
•
Character generators
•
Data security encoders
•
Fault detectors
•
Frequency synthesizers
•
16-bit to 8-bit bus interface
•
Random logic replacement
Fuse Enable Pin: It is recommended that this pin
be left open or connected to ground during normal
operation.
N = Plastic DIP (600mil-wide)
A Package
I5
4
I4
I3
I2
I1
I0
5
6
7
8
9
I6
3
I7 FE V
CC
I8 I9
2
1 28 27 26
25 I10
24 I11
23 I12
22 I13
21 I14
20 I15
19 CE
12
13
14
15
16
17
18
F7 10
F6 11
F5 F4 GND F3 F2 F1 F0
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
28-Pin Plastic Dual In-Line 600mil-wide
28-Pin Plastic Leaded Chip Carrier
3-STATE
PLS100N
PLS100A
OPEN COLLECTOR
PLS101N
PLS101A
DRAWING NUMBER
0413D
0401F
October 22, 1993
49
853–0308 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16
×
48
×
8)
PLS100/PLS101
LOGIC DIAGRAM
(LOGIC TERMS–P)
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
I15
9
8
7
6
5
4
3
2
27
26
25
24
23
22
21
20
S
0
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
47
40 39
32 31
24 23
1615
8 7
0
S
1
S
2
S
3
S
4
S
5
S
6
S
7
18
17
16
15
13
12
11
10
19
F0
F1
F2
F3
F4
F5
F6
F7
CE
NOTES:
1. All AND gate inputs with a blown link float to a logic “1”.
2. All OR gate inputs with a blown fuse float to logic “0”.
3.
Programmable connection.
October 22, 1993
50
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16
×
48
×
8)
PLS100/PLS101
FUNCTIONAL DIAGRAM
I0
TYPICAL CONNECTION
I1
I15
TYPICAL CONNECTION
S
0
F0
S
6
F6
S
7
F7
P
0
P
1
P
47
CE
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
CC
V
IN
V
O
I
IN
I
OUT
T
amb
T
stg
PARAMETER
Supply voltage
Input voltage
Output voltage
Input current
Output current
Operating temperature range
Storage temperature range
RATINGS
+7.0
+5.5
+5.5
±30
+100
0 to +75
–65 to +150
UNIT
V
DC
V
DC
V
DC
mA
mA
°C
°C
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other conditions above
those indicated in the operational and programming specification of the device is not
implied.
THERMAL RATINGS
TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise
ambient to junction
150°C
75°C
75°C
The PLS100 device is also processed to
military requirements for operation over the
military temperature range. For specifications
and ordering information consult the Philips
Semiconductors Military Data Handbook.
October 22, 1993
51
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16
×
48
×
8)
PLS100/PLS101
DC ELECTRICAL CHARACTERISTICS
0°C
≤
T
amb
≤
+75°C, 4.75V
≤
V
CC
≤
5.25V
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
Input voltage
2
V
IH
V
IL
V
IC
High
Low
Clamp
3
V
CC
= MAX
V
CC
= MIN
V
CC
= MIN, I
IN
= –12mA
–0.8
2.0
0.8
–1.2
V
V
V
Output voltage
2
V
CC
= MIN
V
OH
V
OL
High (PLS100)
4
Low
5
I
OH
= –2mA
I
OL
= 9.6mA
2.4
0.35
0.45
V
V
Input current
I
IH
I
IL
High
Low
V
IN
= 5.5V
V
IN
= 0.45V
<1
–10
25
–100
µA
µA
Output current
I
O(OFF)
Hi-Z state (PLS100)
CE = High, V
CC
= MAX
V
OUT
= 5.5V
V
OUT
= 0.45V
I
OS
I
CC
Capacitance
CE = High, V
CC
= 5.0V
C
IN
C
OUT
Input
Output
V
IN
= 2.0V
V
OUT
= 2.0V
8
17
pF
pF
Short circuit (PLS100)
3, 6
V
CC
supply current
7
CE = Low, V
OUT
= 0V
V
CC
= MAX
–15
120
1
–1
40
–40
–70
170
µA
µA
mA
mA
NOTES:
1. All typical values are at V
CC
= 5V, T
amb
= +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one pin at a time.
4. Measured with V
IL
applied to CE and a logic high stored.
5. Measured with a programmed logic condition for which the output test is at a low logic level. Output sink current is applied through a resistor
to V
CC
.
6. Duration of short circuit should not exceed 1 second.
7. I
CC
is measured with the Chip Enable input grounded, all other inputs at 4.5V and the outputs open.
October 22, 1993
52
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16
×
48
×
8)
PLS100/PLS101
AC ELECTRICAL CHARACTERISTICS
0°C < T
amb
< +75°C, 4.75 < V
CC
< 5.25V, R
1
= 470Ω, R
2
= 1kΩ
LIMITS
SYMBOL
Propagation delay
2
t
PD
t
CE
Disable time
t
CD
Chip Disable
3
Output
Chip Enable
15
30
ns
Input
Chip Enable
3
Output
Output
Input
Chip Enable
35
15
50
30
ns
ns
PARAMETER
TO
FROM
MIN
TYP
1
MAX
UNIT
NOTES:
1. All typical values are at V
CC
= 5V. T
amb
= +25°C.
2. All propagation delays are measured and specified under worst case conditions.
3. For 3-State output; output enable times are tested with C
L
= 30pF to the 1.5V level, and S
1
is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
L
= 5pF. High-to-High impedance tests are made to an output
voltage of V
T
= (V
OH
– 0.5V) with S
1
open, and Low-to-High impedance tests are made to the V
T
= (V
OL
+ 0.5V) level with S
1
closed.
VOLTAGE WAVEFORMS
+3.0V
90%
TEST LOAD CIRCUIT
V
CC
10%
+5V
S
1
0V
5ns
+3.0V
90%
t
R
t
F
5ns
C
1
C
2
I
0
F
0
R
1
INPUTS
10%
0V
5ns
5ns
I
15
DUT
R
2
C
L
CE
GND
F
7
OUTPUTS
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of in-
puts and outputs, unless otherwise specified.
Input Pulses
NOTE:
C
1
and C
2
are to bypass V
CC
to GND.
TIMING DEFINITIONS
SYMBOL
t
CE
PARAMETER
Delay between beginning of
Chip Enable Low (with Input
valid) and when Data Output
becomes valid.
Delay between when Chip
Enable becomes High and
Data Output is in off state
(Hi-Z or High).
Delay between beginning of
valid Input (with Chip Enable
Low) and when Data Output
becomes valid.
TIMING DIAGRAM
+3.0V
INPUT
1.5V
0V
+3.0V
t
CD
F0 – F7
t
PD
October 22, 1993
53
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
t
CE
t
PD
CE
1.5V
1.5V
0V
t
CD
V
OH
1.5V
1.5V
V
OL
Read Cycle
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