Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(22
×
42
×
10)
PLS173
DESCRIPTION
The PLS173 is a two-level logic element
consisting of 42 AND gates and 10 OR gates
with fusible link connections for programming
I/O polarity and direction.
All AND gates are linked to 12 inputs (I) and
10 bidirectional I/O lines (B). These yield
variable I/O gate configurations via 10
direction control gates (D), ranging from 22
inputs to 10 outputs.
On-chip T/C buffers couple either True (I, B)
or Complement (I, B) input polarities to all
AND gates, whose outputs can be optionally
linked to all OR gates. Their output polarity, in
turn, is individually programmable through a
set of EX-OR gates for implementing
AND/OR or AND/NOR logic functions.
The PLS173 is field programmable, enabling
the user to quickly generate custom patterns
using standard programming equipment.
Order codes for this device are listed below.
FEATURES
•
I/O propagation delay: 30ns (max.)
•
12 inputs
•
42 AND gates
•
10 OR gates
•
10 bidirectional I/O lines
•
Active-High or -Low outputs
•
42 product terms:
–
32 logic terms
–
10 control terms
PIN CONFIGURATIONS
N Package
I0 1
I1 2
I2 3
I3 4
I4 5
I5 6
I6 7
I7 8
I8 9
I9 10
I10 11
GND 12
N = Plastic DIP (300mil-wide)
24 V
CC
23 B9
22 B8
21 B7
20 B6
19 B5
18 B4
17 B3
16 B2
15 B1
14 B0
13 I11
•
Ni-Cr programmable links
•
Input loading: –100µA (max.)
•
Power dissipation: 750mW (typ.)
•
3-State outputs
•
TTL compatible
APPLICATIONS
A Package
I3
4
I2
3
I1
2
I0 V
CC
B9 B8
1 28 27 26
25 NC
24 B7
23 B6
22 B5
21 B4
20 B3
19 NC
12
I9
13
14
15
16
17
18
•
Random logic
•
Code converters
•
Fault detectors
•
Function generators
•
Address mapping
•
Multiplexing
NC 5
I4 6
I5 7
I6 8
I7 9
I8 10
NC 11
I10 GND I11 B0 B1 B2
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
24-Pin Plastic Dual-In-Line 300mil-wide
28-Pin Plastic Leaded Chip Carrier
ORDER CODE
PLS173N
PLS173A
DRAWING NUMBER
0410D
0401F
October 22, 1993
25
853–0324 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(22
×
42
×
10)
PLS173
LOGIC DIAGRAM
(LOGIC TERMS–P)
I0
I1
I2
I3
I4
I5
I6
I7
I8
1
2
3
4
5
6
7
8
9
(CONTROL TERMS)
I9 10
I10 11
I11 13
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
S
9
X
9
X
8
X
7
X
6
X
5
X
4
X
3
X
2
X
1
31
24 23
16 15
8 7
0
X
0
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
S
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
23 B9
22 B8
21 B7
20 B6
19 B5
18 B4
17 B3
16 B2
15 B1
14 B0
NOTES:
1. All programmed ‘AND’ gate locations are pulled to logic “1”.
2. All programmed ‘OR’ gate locations are pulled to logic “0”.
3.
Programmable connection.
October 22, 1993
26
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(22
×
42
×
10)
PLS173
FUNCTIONAL DIAGRAM
P
31
I0
P
0
D
0
D
9
LOGIC FUNCTION
TYPICAL PRODUCT TERM:
Pn = A
⋅
B
⋅
C
⋅
D
⋅
. . .
TYPICAL LOGIC FUNCTION:
AT OUTPUT POLARITY = H
Z = P0 + P1 + P2 . . .
AT OUTPUT POLARITY + L
Z = P0 + P1 + P2 + . . .
I11
B0
Z = P0
⋅
P1
⋅
P2
⋅
. . .
B9
NOTES:
1. For each of the 10 outputs, either function Z
(Active-High) or Z (Active-Low) is available, but not
both. The desired output polarity is programmed
via the EX-OR gates.
2. ZX, A, B, C, etc. are user defined connections to
fixed inputs (I), and bidirectional pins (B).
S
9
X
9
B9
S
0
X
0
B0
ABSOLUTE MAXIMUM RATINGS
1
RATING
SYMBOL
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
amb
T
stg
PARAMETER
Supply voltage
Input voltage
Output voltage
Input currents
Output currents
Operating free-air temperature range
Storage temperature range
0
–65
–30
Min
Max
+7
+5.5
+5.5
+30
+100
+75
+150
UNIT
V
DC
V
DC
V
DC
mA
mA
°C
°C
THERMAL RATINGS
TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise
ambient to junction
150
°
C
75
°
C
75
°
C
The PLS173 is also processed to military
requirements for operation over the military
temperature range. For specifications and
ordering information, consult the Philips
Semiconductors Military Data Handbook.
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied.
October 22, 1993
27
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(22
×
42
×
10)
PLS173
DC ELECTRICAL CHARACTERISTICS
0°C
≤
T
amb
≤
+75°C, 4.75
≤
V
CC
≤
5.25V
LIMITS
SYMBOL
Input voltage
2
V
IL
V
IH
V
IC
Low
High
Clamp
3
V
CC
= MIN
V
CC
= MAX
V
CC
= MIN, I
IN
= –12mA
2.0
–0.8
–1.2
0.8
V
V
V
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
Output voltage
2
V
CC
= MIN
V
OL
V
OH
Low
4
High
5
I
OL
= 15mA
I
OH
= –2mA
2.4
0.5
V
V
Input current
9
V
CC
= MAX
I
IL
I
IH
Low
High
V
IN
= 0.45V
V
IN
= V
CC
–100
40
µA
µA
Output current
V
CC
= MAX
I
O(OFF)
Hi-Z state
8
V
OUT
= 5.5V
V
OUT
= 0.45V
I
OS
I
CC
Capacitance
V
CC
= 5V
I
IN
C
B
Input
I/O
V
IN
= 2.0V
V
B
= 2.0V
8
15
pF
pF
Short circuit
3, 5, 6
V
CC
supply current
7
V
OUT
= 0V
V
CC
= MAX
–15
150
80
–140
–70
170
mA
mA
µA
NOTES:
1. All typical values are at V
CC
= 5V, T
amb
= +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with inputs V
IL
applied to I
11
. Pins 1–5 = 0V, Pins 6–10 = 4.5V, Pin 11 = 0V and Pin 13 = 10V.
5. Same conditions as Note 4 except Pin 11 = +10V.
6. Duration of short circuit should not exceed 1 second.
7. I
CC
is measured with I
0
and I
1
= 0V, and I
2
– I
11
and B
0
– B
9
= 4.5V. Part in Virgin State.
8. Leakage values are a combination of input and output leakage.
9. I
IL
and I
IH
limits are for dedicated inputs only (I
0
– I
11
).
October 22, 1993
28
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(22
×
42
×
10)
PLS173
AC ELECTRICAL CHARACTERISTICS
0°C
≤
T
amb
≤
+75°C, 4.75
≤
V
CC
≤
5.25V, R
1
= 470Ω, R
2
= 1kΩ
TEST
SYMBOL
t
PD
t
OE
t
OD
PARAMETER
Propagation delay
2
Output enable
1
Output disable
1
FROM
Input
±
Input
±
Input
±
TO
Output
±
Output –
Output +
CONDITION
C
L
= 30pF
C
L
= 30pF
C
L
= 5pF
MIN
LIMITS
TYP
20
20
20
MAX
30
30
30
UNIT
ns
ns
ns
NOTES:
1. For 3-State output; output enable times are tested with C
L
= 30pF to the 1.5V level, and S
1
is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
L
= 5pF. High-to-High impedance tests are made to an output
voltage of V
T
= (V
OH
– 0.5V) with S
1
open, and Low-to-High impedance tests are made to the V
T
= (V
OL
+ 0.5V) level with S
1
closed.
2. All propagation delays are measured and specified under worst case conditions.
VOLTAGE WAVEFORM
+3.0V
90%
TEST LOAD CIRCUIT
V
CC
10%
+5V
S
1
0V
5ns
+3.0V
90%
t
R
t
F
5ns
C
1
C
2
I0
B
Y
R
1
INPUTS
10%
0V
5ns
5ns
I11
B
W
DUT
R
2
C
L
B
X
GND
B
Z
OUTPUTS
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
Input Pulses
NOTE:
C
1
and C
2
are to bypass V
CC
to GND.
TIMING DEFINITIONS
SYMBOL
t
PD
t
OD
PARAMETER
Propagation delay between
input and output.
Delay between input change
and when output is off (Hi-Z
or High).
Delay between input change
and when output reflects
specified output level.
TIMING DIAGRAM
+3V
I, B
1.5V
1.5V
1.5V
0V
V
OH
B
1.5V
V
T
t
OD
t
OE
1.5V
V
OL
t
PD
t
OE
October 22, 1993
29
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