Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(18
×
42
×
10)
PLUS153B/D
DESCRIPTION
The PLUS153 PLDs are high speed,
combinatorial Programmable Logic Arrays.
The Philips Semiconductors state-of-the-art
Oxide Isolated Bipolar fabrication process is
employed to produce propagation delays as
short as 12ns.
The 20-pin PLUS153 devices have a
programmable AND array and a
programmable OR array. Unlike PAL
®
devices, 100% product term sharing is
supported. Any of the 32 logic product terms
can be connected to any or all of the 10
output OR gates. Most PAL ICs are limited to
7 AND terms per OR function; the PLUS153
devices can support up to 32 input wide OR
functions.
The polarity of each output is
user-programmable as either active-High or
active-Low, thus allowing AND-OR or
AND-NOR logic implementation. This feature
adds an element of design flexibility,
particularly when implementing complex
decoding functions.
The PLUS153 devices are
user-programmable using one of several
commercially available, industry standard
PLD programmers.
FEATURES
•
I/O propagation delays (worst case)
–
PLUS153B – 15ns max.
–
PLUS153D – 12ns max.
PIN CONFIGURATIONS
N Package
I0
I1
I2
I3
I4
I5
I6
I7
B0
1
2
3
4
5
6
7
8
9
20 V
CC
19 B9
18 B8
17 B7
16 B6
15 B5
14 B4
13 B3
12 B2
11 B1
•
Functional superset of 16L8 and most
other 20-pin combinatorial PAL devices
•
Two programmable arrays
–
Supports 32 input wide OR functions
•
8 inputs
•
10 bi-directional I/O
•
42 AND gates
–
32 logic product terms
–
10 direction control terms
GND 10
•
Programmable output polarity
–
Active-High or Active-Low
N = Plastic Dual In-Line Package (300mil-wide)
•
Security fuse
•
3-State outputs
•
Power dissipation: 750mW (typ.)
•
TTL Compatible
APPLICATIONS
I3
I4
I5
I6
I7
4
5
6
7
8
A Package
I2
3
I1
2
I0 V
CC
B9
1
20
19
18 B8
17 B7
16 B6
15 B5
14 B4
9
10
11
12
13
•
Random logic
•
Code converters
•
Fault detectors
•
Function generators
•
Address mapping
•
Multiplexing
t
PD
(MAX)
15ns
12ns
15ns
12ns
B0 GND B1 B2 B3
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic Dual-In-Line 300mil-wide
20-Pin Plastic Dual-In-Line 300mil-wide
20-Pin Plastic Leaded Chip Carrier
20-Pin Plastic Leaded Chip Carrier
ORDER CODE
PLUS153BN
PLUS153DN
PLUS153BA
PLUS153DA
DRAWING NUMBER
0408D
0408D
0400E
0400E
®PAL
is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices Corporation.
October 22, 1993
9
853–1285 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(18
×
42
×
10)
PLUS153B/D
LOGIC DIAGRAM
(LOGIC TERMS–P)
I0
I1
I2
I3
I4
I5
I6
I7
1
2
3
4
5
6
7
8
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
(CONTROL TERMS)
S
9
X
9
X
8
X
7
X
6
X
5
X
4
X
3
X
2
X
1
31
24 23
16 15
8 7
0
X
0
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
S
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
19 B9
18 B8
17 B7
16 B6
15 B5
14 B4
13 B3
12 B2
11 B1
9 B0
NOTES:
1. All programmed ‘AND’ gate locations are pulled to logic “1”.
2. All programmed ‘OR’ gate locations are pulled to logic “0”.
3.
Programmable connection.
October 22, 1993
10
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(18
×
42
×
10)
PLUS153B/D
FUNCTIONAL DIAGRAM
P
31
I0
P
0
D
0
D
9
I7
B0
B9
S
9
X
9
B9
S
0
X
0
B0
ABSOLUTE MAXIMUM RATINGS
1
RATING
SYMBOL
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
amb
T
stg
PARAMETER
Supply voltage
Input voltage
Output voltage
Input currents
Output currents
Operating free-air temperature range
Storage temperature range
0
–65
–30
MIN
MAX
+7
+5.5
+5.5
+30
+100
+75
+150
UNIT
V
DC
V
DC
V
DC
mA
mA
°C
°C
THERMAL RATINGS
TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise
ambient to junction
150
°
C
75
°
C
75
°
C
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other condition above
those indicated in the operational and programming specification of the device is not
implied.
October 22, 1993
11
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(18
×
42
×
10)
PLUS153B/D
DC ELECTRICAL CHARACTERISTICS
0°C
≤
T
amb
≤
+75°C, 4.75
≤
V
CC
≤
5.25V
LIMITS
SYMBOL
Input voltage
2
V
IL
V
IH
V
IC
Low
High
Clamp
V
CC
= MIN
V
CC
= MAX
V
CC
= MIN, I
IN
= –12mA
2.0
–0.8
–1.2
0.8
V
V
V
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
Output voltage
2
V
CC
= MIN
V
OL
V
OH
Low
4
High
5
I
OL
= 15mA
I
OH
= –2mA
2.4
0.5
V
V
Input current
9
V
CC
= MAX
I
IL
I
IH
Low
High
V
IN
= 0.45V
V
IN
= V
CC
–100
40
µA
µA
Output current
V
CC
= MAX
I
O(OFF)
Hi-Z state
8
V
OUT
= 2.7V
V
OUT
= 0.45V
I
OS
I
CC
Capacitance
V
CC
= 5V
C
IN
C
B
Input
I/O
V
IN
= 2.0V
V
B
= 2.0V
8
15
pF
pF
Short circuit
3, 5, 6
V
CC
supply current
7
V
OUT
= 0V
V
CC
= MAX
–15
150
80
–140
–70
200
mA
mA
µA
NOTES:
1. All typical values are at V
CC
= 5V, T
amb
= +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with inputs I0 – I2 = 0V, inputs I3 – I5 = 4.5V, inputs I7 = 4.5V and I6 = 10V. For outputs B0 – B4 and for outputs B5 – B9 apply the
same conditions except I7 = 0V.
5. Same conditions as Note 4 except I7 = +10V.
6. Duration of short circuit should not exceed 1 second.
7. I
CC
is measured with inputs I0 – I7 and B0 – B9 = 0V.
8. Leakage values are a combination of input and output leakage.
9. I
IL
and I
IH
limits are for dedicated inputs only (I0 – I7).
October 22, 1993
12
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(18
×
42
×
10)
PLUS153B/D
AC ELECTRICAL CHARACTERISTICS
0°C
≤
T
amb
≤
+75°C, 4.75V
≤
V
CC
≤
5.25V, R
1
= 300Ω, R
2
= 390Ω
LIMITS
SYMBOL
PARAMETER
FROM
TO
TEST
CONDITION
t
PD
t
OE
t
OD
Propagation Delay
2
Output Enable
1
Output Disable
1
Input +/–
Input +/–
Input +/–
Output +/–
Output –
Output +
C
L
= 30pF
C
L
= 30pF
C
L
= 5pF
MIN
PLUS153B
TYP
11
11
11
MAX
15
15
15
MIN
PLUS153D
TYP
10
10
10
MAX
12
12
12
ns
ns
ns
UNIT
NOTES:
1. For 3-State output; output enable times are tested with C
L
= 30pF to the 1.5V level, and S
1
is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
L
= 5pF. High-to-High impedance tests are made to an output
voltage of V
T
= (V
OH
– 0.5V) with S
1
open, and Low-to-High impedance tests are made to the V
T
= (V
OL
+ 0.5V) level with S
1
closed.
2. All propagation delays are measured and specified under worst case conditions.
VOLTAGE WAVEFORMS
+3.0V
90%
TEST LOAD CIRCUIT
V
CC
10%
+5V
S
1
0V
5ns
+3.0V
90%
t
R
t
F
5ns
C
1
C
2
I0
B
Y
R
1
INPUTS
10%
0V
5ns
5ns
I7
B
W
DUT
R
2
C
L
B
X
GND
B
Z
OUTPUTS
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
Input Pulses
NOTE:
C
1
and C
2
are to bypass V
CC
to GND.
TIMING DEFINITIONS
SYMBOL
t
PD
t
OD
PARAMETER
Propagation delay between
input and output.
Delay between input change
and when output is off (Hi-Z
or High).
Delay between input change
and when output reflects
specified output level.
TIMING DIAGRAM
+3V
I, B
1.5V
1.5V
1.5V
0V
V
OH
B
1.5V
V
T
t
OD
t
OE
1.5V
V
OL
t
PD
t
OE
October 22, 1993
13
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
