Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH4S64CWZTJ is 4194304-word by 64-bit
Synchronous DRAM module. This consists of sixteen
industry standard 2Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
85pin
1pin
94pin
95pin
10pin
11pin
FEATURES
Frequency
-12
-15
83MHz
67MHz
CLK Access Time
8.5ns
9.5ns
Back side
Front side
-1
Utilizes industry standard 2M x 8 Synchronous DRAMs
100MH
8.5n
0
TSOP and industry standard EEPROM in TSSOP
z
s
168-pin (84-pin dual in-line package)
124pin
125pin
40pin
41pin
single 3.3V±0.3V power supply
Clock frequency 83MHz/67MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA(Bank Address)
/CAS latency- 2/3/4(programmable)
Burst length- 1/4(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
168pin
84pin
APPLICATION
main memory or graphic memory in computer systems
SPD table
Byte No.
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 126 127
06 01 05 02 04 01 01 83 06
06 01 05 02 04 01 01 66 06
MH4S64CWZTJ-12 80 08 04 0C 09 02
MH4S64CWZTJ-15 80 08 04 0C 09 02
40 00 01 C0 85 00 80 00
40 00 01 F0 95 00 80 00
MIT-DS-0053-0.2
MITSUBISHI
ELECTRIC
( 1 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
PIN NO.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
PIN NAME
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
NC
NC
VSS
NC
NC
VDD
/CAS
DQMB4
DQMB5
/S1
/RAS
VSS
A1
A3
A5
A7
A9
BA
NC
VDD
CK1
NC
PIN NO.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
PIN NAME
VSS
CKE
/S3
DQMB6
DQMB7
NC
VDD
NC
NC
NC
NC
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
NC
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
NC
NC
SA0
SA1
SA2
VDD
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
PIN NAME
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
NC
NC
VSS
NC
NC
VDD
/WE0
DQMB0
DQMB1
/S0
NC
VSS
A0
A2
A4
A6
A8
A10
NC
VDD
VDD
CK0
PIN NO.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
PIN NAME
VSS
NC
/S2
DQMB2
DQMB3
NC
VDD
NC
NC
NC
NC
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
NC
NC
NC
SDA
SCL
VDD
NC = No Connection
MIT-DS-0053-0.2
MITSUBISHI
ELECTRIC
( 2 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
Block Diagram
CK0
/S1
/S0
DQMB0
DQM /CS CK0
DQM /CS CK0
DQMB4
DQM /CS CK0
DQM /CS CK0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4 D12
I/O 5
I/O 6
I/O 7
DQM /CS CK0
DQM /CS CK0
DQM /CS CK0
DQM /CS CK0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CK1
/S3
/S2
DQMB2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D13
DQMB6
DQM /CS CK0
DQM /CS CK0
DQM /CS CK0
DQM /CS CK0
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D10
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4 D14
I/O 5
I/O 6
I/O 7
DQM /CS CK0
DQM /CS CK0
DQM /CS CK0
DQM /CS CK0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CKE
/RAS
/CAS
/WE
BA,A<10:0>
Vcc
Vss
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4 D11
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D15
D0 - D15
D0 - D15
D0 - D15
D0 - D15
D0 - D15
D0 - D15
D0 - D15
SERIAL PD
SCL
A0
A1
A2
SA0 SA1 SA2
SDA
MIT-DS-0053-0.2
MITSUBISHI
ELECTRIC
( 3 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
CK
(CK0 & CK1)
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
Combination of /RAS,/CAS,/WE defines basic commands.
A0-10 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-10.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA is not simply BA.BA specifies the bank
to which a command is applied.BA must be set with
ACT,PRE,READ,WRITE commands
CKE
Input
/S
(/S0 ~ /S3)
/RAS,/CAS,/WE
Input
Input
A0-10
Input
BA
Input
DQ0-63
Data In and Data out are referenced to the rising edge of
Input/Output CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
DQMB0-7
Input
Vdd,Vss
SLA
SDA
SA0-3
Power Supply Power Supply for the memory mounted module.
Input
Output
Input
Serial clock for serial PD
Serial data for serial PD
Address input for serial PD
MIT-DS-0053-0.2
MITSUBISHI
ELECTRIC
( 4 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH4S64CWZTJ provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @refresh
command
Precharge Option @precharge or read/write
command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all,
PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0053-0.2
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ELECTRIC
( 5 / 44 )
Aug.8.1996
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