74VHCT00A — Quad 2-Input NAND Gate
December 2007
74VHCT00A
Quad 2-Input NAND Gate
Features
■
High speed: t
PD
=
5.0ns (Typ.) at T
A
=
25°C
■
High noise immunity: V
IH
=
2.0V, V
IL
=
0.8V
■
Power down protection is provided on all inputs and
General Description
The VHCT00A is an advanced high-speed CMOS
2-Input NAND Gate fabricated with silicon gate CMOS
technology. It achieves the high-speed operation similar
to equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. The internal circuit is
composed of 3 stages, including buffer output, which
provide high noise immunity and stable output.
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with V
CC
=
0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V
to 5V systems and two supply systems such as battery
backup.
outputs
■
Low noise: V
OLP
=
0.8V (Max.)
■
Low power dissipation: I
CC
=
2A (Max.) at T
A
=
25°C
■
Pin and function compatible with 74HCT00
Ordering Information
Order Number
74VHCT00AM
74VHCT00ASJ
74VHCT00AMTC
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012,
0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1997 Fairchild Semiconductor Corporation
74VHCT00A Rev. 1.4.0
www.fairchildsemi.com
74VHCT00A — Quad 2-Input NAND Gate
Connection Diagram
Logic Symbol
Pin Description
Pin Names
A
n
, B
n
O
n
Inputs
Outputs
Truth Table
Description
A
L
L
H
H
B
L
H
L
H
O
H
H
H
L
©1997 Fairchild Semiconductor Corporation
74VHCT00A Rev. 1.4.0
www.fairchildsemi.com
2
74VHCT00A — Quad 2-Input NAND Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
Supply Voltage
DC Input Voltage
DC Output Voltage
Note 1
Note 2
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
Input Diode Current
Output Diode Current
(3)
DC Output Current
DC V
CC
/ GND Current
Storage Temperature
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–0.5V to 7.0V
–20mA
±20mA
±25mA
±50mA
–65°C to +150°C
260°C
Lead Temperature (Soldering, 10 seconds)
Recommended Operating Conditions
(4)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
V
OUT
Supply Voltage
Input Voltage
Output Voltage
Note 1
Note 2
T
OPR
t
r
, t
f
Operating Temperature
Parameter
Rating
4.5V to +5.5V
0V to +5.5V
0V to V
CC
0V to 5.5V
–40°C to +85°C
0ns/V
∼
20ns/V
Input Rise and Fall Time, V
CC
=
5.0V ±0.5V
Notes:
1. HIGH or LOW state. I
OUT
absolute maximum rating must be observed.
2. V
CC
=
0V.
3. V
OUT
<
GND, V
OUT
>
V
CC
(Outputs Active).
4. Unused inputs must be held HIGH or LOW. They may not float.
©1997 Fairchild Semiconductor Corporation
74VHCT00A Rev. 1.4.0
www.fairchildsemi.com
3
74VHCT00A — Quad 2-Input NAND Gate
DC Electrical Characteristics
T
A
=
25°C
Symbol
V
IH
V
IL
V
OH
V
OL
I
IN
I
CC
I
CCT
I
OFF
T
A
=
–40°C
to +85°C
Min.
2.0
2.0
0.8
0.8
0.8
0.8
4.40
3.80
0.1
0.36
±0.1
2.0
1.35
0.5
0.1
0.44
±1.0
20.0
1.50
5.0
µA
µA
mA
µA
V
V
V
Parameter
HIGH Level Input
Voltage
LOW Level Input
Voltage
HIGH Level Output
Voltage
LOW Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
Maximum I
CC
/ Input
Output Leakage
Current (Power
Down State)
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
4.5
0 – 5.5
5.5
5.5
0.0
Conditions
Min.
2.0
2.0
Typ.
Max.
Max. Units
V
V
IN
=
V
IH
or V
IL
V
IN
=
V
IH
or V
IL
I
OH
=
–50µA
I
OH
=
–8mA
I
OL
=
50µA
I
OL
=
8mA
4.40
3.94
4.50
0.0
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
V
IN
=
3.4V, Other
Inputs
=
V
CC
or GND
V
OUT
=
5.5V
Noise Characteristics
T
A
=
25°C
Symbol
V
OLP(5)
V
OLV
(5)
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
Conditions
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
V
CC
(V)
5.0
5.0
5.0
5.0
Typ.
0.4
–0.4
Limit
0.8
–0.8
2.0
0.8
Units
V
V
V
V
V
IHD(5)
V
ILD(5)
Note:
5. Parameter guaranteed by design.
AC Electrical Characteristics
T
A
=
25°C
Symbol
t
PLH
, t
PHL
C
IN
C
PD
T
A
=
–40°C
to +85°C
Min.
1.0
1.0
Parameter
Propagation Delay
Input Capacitance
Power Dissipation
Capacitance
V
CC
(V)
5.0 ± 0.5
Conditions
C
L
=
15pF
C
L
=
50pF
V
CC
=
Open
(6)
Min.
Typ.
5.0
5.5
4
17
Max.
6.9
7.9
10
Max.
8.0
9.0
10
Units
ns
pF
pF
Note:
6. C
PD
is defined as the value of the internal equivalent capacitance, which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
I
CC
(Opr.)
=
C
PD
• V
CC
• f
IN
+ I
CC
/ 4 (per gate)
©1997 Fairchild Semiconductor Corporation
74VHCT00A Rev. 1.4.0
www.fairchildsemi.com
4
74VHCT00A — Quad 2-Input NAND Gate
Physical Dimensions
8.75
8.50
7.62
14
8
B
A
0.65
5.60
6.00
4.00
3.80
PIN ONE
INDICATOR
1
7
1.70
1.27
1.27
(0.33)
0.51
0.35
0.25
M
LAND PATTERN RECOMMENDATION
C B A
1.75 MAX
1.50
1.25
0.25
0.10
C
0.10 C
SEE DETAIL A
0.25
0.19
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
X 45°
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.50
0.25
R0.10
R0.10
8°
0°
0.90
0.50
(1.04)
DETAIL A
SCALE: 20:1
SEATING PLANE
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1997 Fairchild Semiconductor Corporation
74VHCT00A Rev. 1.4.0
www.fairchildsemi.com
5
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