Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
FEATURES
•
Independent registers for A and B buses
•
Multiplexed real-time and stored data
•
3-State outputs
•
Live insertion/extraction permitted
•
Power-up 3-State
•
Power-up reset
•
Output capability: +64mA/–32mA
•
Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT652A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT652A transceiver/register consists of bus transceiver
circuits with 3-State outputs, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from the input
bus or the internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes High. Output
Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for
bus management.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
PARAMETER
Propagation delay
CPBA to An or CPAB to Bn
Input capacitance
I/O capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled;
V
O
= 0V or V
CC
Outputs disabled; V
CC
=5.5V
TYPICAL
3.7
4.3
4
7
110
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
24-pin plastic DIP
24-pin plastic SOL
24-pin plastic SSOP Type II
24-pin plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
ORDER CODE
74ABT652AN
74ABT652AD
74ABT652ADB
74ABT652APW
DRAWING NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
CPAB
SAB
OEAB
A0
A1
A2
A3
A4
A5
A6
A7
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CPBA
SBA
OEBA
B0
B1
B2
B3
B4
B5
B6
B7
PIN DESCRIPTION
PIN NUMBER
1, 23
2, 22
3, 21
4, 5, 6, 7,
8, 9, 10, 11
20, 19, 18, 17,
16, 15, 14, 13
12
24
SYMBOL
CPAB /
CPBA
SAB /
SBA
OEAB /
OEBA
A0 – A7
B0 – B7
GND
V
CC
FUNCTION
A to B clock input / B to A clock input
A to B select input / B to A select
input
A to B Output Enable input /
B to A Output Enable input
(active–Low)
Data inputs/outputs (A side)
Data inputs/outputs (B side)
Ground (0V)
Positive supply voltage
SA00094
1995 Apr 19
1
853-1614 15144
Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
LOGIC SYMBOL
4
5
6
7
8
9
10
11
LOGIC SYMBOL (IEEE/IEC)
21
3
EN1 [BA]
EN2 [AB]
C4
G5
C6
G7
A0
A1
A2
A3
A4
A5
A6
A7
23
22
1
2
23
22
2
1
CPBA
SBA
SAB
CPAB
OEAB
OEBA
3
21
4
w1
1
6D
7
7
5
5 1
4D
20
B0
B1
B2
B3
B4
B5
B6
B7
1
w1
2
20
19
18
17
16
15
14
13
5
6
19
18
17
16
15
14
13
SA00095
7
8
9
10
11
SA00096
FUNCTION TABLE
INPUTS
OEAB
L
L
X
H
L
L
L
L
H
H
H
H
L
X
↑
*
**
=
=
=
=
OEBA
H
H
H
H
X
L
L
L
H
H
L
CPAB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
CPBA
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
SAB
X
X
X
**
X
X
X
X
L
H
H
SBA
X
X
X
X
X
**
L
H
X
X
H
An
Input
Input
Unspecified
output*
Output
Input
Output
DATA I/O
Bn
Input
Unspecified
output*
Input
Input
Output
Output
OPERATING MODE
Isolation
Store A and B data
Store A, Hold B
Store A in both registers
Hold A, Store B
Store B in both registers
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Store A data to B bus
Stored A data to B bus
Stored B data to A bus
High voltage level
Low voltage level
Don’t care
Low-to-High clock transition
The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
If both Select controls (SAB and SBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be
staggered in order to load both registers.
1995 Apr 19
2
Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74ABT652A.
The select pins determine whether data is stored or transferred
through the device in real time.
The output enable pins determine the direction of the data flow.
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A OR B
A
B
A
B
A
B
A
B
OEABOEBA CPAB CPBA SAB SBA
L
L
X
X
X
L
}
H
H
OEABOEBA CPAB CPBA SAB SBA
X
X
L
X
}
X
L
L
H
X
H
OEABOEBA CPAB CPBA SAB SBA
↑
X
↑
X
↑
↑
X
X
X
X
X
X
}
H
L
OEABOEBA CPAB CPBA SAB SBA
H|L H|L
H
H
}
SA00097
1995 Apr 19
3
Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
LOGIC DIAGRAM
21
OEBA
3
OEAB
23
CPBA
22
SBA
1
CPAB
2
SAB
1of 8 Channels
1D
C1
Q
A0
4
1D
C1
Q
20
B0
A1
A2
A3
A4
A5
A6
A7
5
6
7
8
9
10
11
DETAIL A X 7
19
18
17
16
15
14
13
B1
B2
B3
B4
B5
B6
B7
SA00098
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1995 Apr 19
4
Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
PARAMETER
Min
4.5
0
2.0
0.8
–32
64
10
+85
Max
5.5
V
CC
V
V
V
V
mA
mA
ns/V
°C
UNIT
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
Min
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
OH
High–level output voltage
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
V
OL
V
RST3
I
I
Low–level output voltage
Power-up output low voltage
Input leakage
current
I
OFF
I
PU
/I
PD
I
IH
+ I
OZH
I
IL
+ I
OZL
I
CEX
I
O
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current per
input pin
2
Quiescent supply current
Control pins
Data pins
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
CC
= 2.1V; V
O
= 0.5V; V
I
= GND or V
CC
;
V
OE
= Don’t care; V
OE
= Don’t care
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND; V
CC
= 5.5V
–40
2.5
3.0
2.0
Typ
–0.9
3.0
3.5
2.4
0.3
0.13
±0.01
±5
±5.0
±5.0
5.0
–5.0
5.0
–65
110
20
110
0.3
0.55
0.55
±1.0
±100
±100
±50
50
–50
50
–180
250
30
250
1.5
–40
Max
–1.2
2.5
3.0
2.0
0.55
0.55
±1.0
±100
±100
±50
50
–50
50
–180
250
30
250
1.5
T
amb
= –40°C
to +85°C
Min
Max
–1.2
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
mA
UNIT
Power-off leakage current
Power-up/down 3-State
output current
4
3–State output High current
3–State output Low current
Output High leakage current
Output current
1, 5
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V, with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V
±
10%, a
transition time of up to 100µsec is permitted.
5. This data sheet limit may vary among suppliers.
1995 Apr 19
5
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