74ACTQ18825 18-Bit Buffer/Line Driver with 3-STATE Outputs
September 1991
Revised January 2000
74ACTQ18825
18-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ18825 contains eighteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is byte controlled. Each byte
has separate 3-STATE control inputs which can be shorted
together for full 18-bit operation.
The ACTQ18825 utilizes Fairchild FACT Quiet Series™
technology to guarantee quiet output switching and
improved dynamic threshold performance. FACT Quiet
Series features GTO™ output control and undershoot cor-
rector for superior performance.
Features
s
Utilizes Fairchild FACT Quiet Series technology
s
Broadside pinout allows for easy board layout
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin output skew
s
Separate control logic for each byte
s
Extra data width for wider address/data paths or buses
carrying parity
s
Outputs source/sink 24 mA
s
Additional specs for Multiple Output Switching
s
Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
74ACTQ18825SSC
74ACTQ18825MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
I
0
–I
17
O
0
–O
17
Description
Output Enable Input (Active LOW)
Inputs
Outputs
FACT™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010955
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74ACTQ18825
Connection Diagram
Functional Description
The ACTQ18825 contains eighteen non-inverting buffers
with 3-STATE standard outputs. The device is byte con-
trolled with each byte functioning identically, but indepen-
dently of the other. The control pins may be shorted
together to obtain full 18-bit operation. The 3-STATE out-
puts are controlled by an Output Enable (OE
n
) input for
each byte. When OE
n
is LOW, the outputs are in 2-state
mode. When OE
n
is HIGH, the outputs are in the high
impedance mode, but this does not interfere with entering
new data into the inputs.
Truth Table
Inputs
Outputs
Byte 1 (0:8) Byte 2 (8:17) I
0
–I
8
I
9
–I
17
O
0
–O
8
O
9
–O
17
OE
1
L
H
X
L
L
H
L
OE
2
L
X
H
L
L
H
L
OE
3
L
L
L
H
X
H
L
OE
4
L
L
L
X
H
H
L
H
X
X
L
H
X
L
H
L
H
X
X
X
L
H
Z
Z
L
H
Z
L
H
L
H
Z
Z
Z
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
HIGH Impedance
Logic Diagram
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2
74ACTQ18825
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+0.5V
DC Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
Per Output Pin
Storage Temperature
ESD Last Passing Voltage (Min)
±50
mA
−65°C
to
+150°C
4000V
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
±50
mA
−20
mA
+20
mA
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (∆V∆t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT™ circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
125 mV/ns
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Minimum HIGH
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
Parameter
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW
Output Voltage
4.5
5.5
4.5
5.5
I
OZ
I
IN
I
CCT
I
CC
I
OLD
I
OHD
V
OLP
V
OLV
V
OHP
V
OHV
V
IHD
V
ILD
Maximum 3-STATE
Leakage Current
Maximum Input Leakage Current
Maximum I
CC
/Input
Maximum Quiescent Supply Current
Minimum Dynamic
Output Current (Note 2)
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Maximum Overshoot
Minimum V
CC
V
CC
Droop
Minimum HIGH Dynamic Input Voltage Level
Maximum LOW Dynamic Input Voltage Level
5.0
5.0
5.0
0.5
−0.5
0.8
−0.8
5.5
5.5
5.5
5.5
5.5
0.6
8.0
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.5
±
0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±5.0
±
1.0
1.5
80.0
75
−75
µA
µA
mA
µA
mA
mA
V
V
V
V
V
V
V
V
OUT
=
0.1V
or V
CC
−0.1V
V
OUT
=
0.1V
or V
CC
−0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 2)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
, GND
V
I
=
V
CC
−2.1V
V
IN
=
V
CC
or GND
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 4)(Note 6)
5.0
5.0
5.0
V
OH
−
1.0 V
OH
−
1.8
1.7
1.2
2.0
0.8
V
V
V
Figure 1, Figure 2
(Note 4)(Note 6)
(Note 4)(Note 7)
(Note 4)(Note 7)
Units
Conditions
V
OH
+
1.0 V
OH
+
1.5
Note 2:
All outputs loaded; thresholds associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
Worst case package.
Note 5:
Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW.
Note 6:
Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH.
Note 7:
Maximum number of data inputs (n) switching (n-1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD).
3
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74ACTQ18825
AC Electrical Characteristics
V
CC
Symbol
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
Parameter
Propagation Delay
Data to Output
Output Enable
Time
Output Disable
Time
5.0
5.0
(V)
(Note 8)
5.0
Min
2.0
2.0
2.0
2.0
1.5
1.5
T
A
= +25°C
C
L
=
50 pF
Typ
5.3
5.6
6.3
6.5
4.5
5.1
Max
8.4
8.7
9.6
9.7
7.3
8.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
2.0
2.0
2.0
2.0
1.5
1.5
Max
9.0
9.2
10.3
10.4
7.6
8.8
ns
ns
ns
Units
Note 8:
Voltage Range 5.0 is 5.0V
±
0.5V.
Extended AC Electrical Characteristics
T
A
= −40°C
to
+85°C
V
CC
=
Com
Symbol
Parameter
C
L
=
50 pF
16 Outputs Switching
(Note 9)
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
(Note 13)
t
OSLH
(Note 13)
t
OST
(Note 13)
Pin to Pin Skew
HL Data to Output
Pin to Pin Skew
LH Data to Output
Pin to Pin Skew
LH/HL Data to Output
Output Disable Time
Propagation Delay
Data to Output
Output Enable Time
6.5
5.5
6.1
6.5
3.1
3.5
Typ
8.0
6.5
7.6
7.8
5.0
5.2
Max
9.8
8.9
9.2
9.4
6.1
6.5
1.5
2.0
2.0
(Note 11)
(Note 12)
Min
(Note 10)
Max
ns
ns
ns
ns
ns
ns
T
A
= −40°C
to
+85°C
V
CC
=
Com
C
L
=
250 pF
Units
Note 9:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 10:
This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 11:
3-STATE delays are load dominated and have been excluded from the datasheet.
Note 12:
The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 13:
Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
).
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Pin Capacitance
Power Dissipation Capacitance
Typ
4.5
95
Units
pF
pF
V
CC
=
5.0V
V
CC
=
5.0V
Conditions
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4
74ACTQ18825
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure V
OLP
and V
OLV
on the quiet output during the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case transition for active and enable
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
ILD
and V
IHD
:
• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, V
IL
, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
• Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
Note 14:
V
OHV
and V
OLP
are measured with respect to ground refer-
ence.
Note 15:
Input pulses have the following characteristics: f
=
1 MHz,
t
r
=
3 ns, t
f
=
3 ns, skew
<
150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
5
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