INTEGRATED CIRCUITS
DATA SHEET
74AVC16245
16-bit transceiver with direction pin;
3-state (3.6 V tolerant)
Product specification
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC24
1999 Nov 15
Philips Semiconductors
Product specification
16-bit transceiver with direction pin; 3-state
(3.6 V tolerant)
FEATURES
•
Wide supply voltage range from 1.2 to 3.6 V
•
Complies with JEDEC standard no. 8-1A/5/7
•
CMOS low power consumption
•
Input/output tolerant up to 3.6 V
•
Dynamic Controlled Output (DCO) circuit dynamically
changes output impedance, resulting in noise reduction
without speed degradation
•
Low inductance multiple power and ground pins for
minimum noise and ground bounce
•
Power off disables outputs, permitting live insertion.
DESCRIPTION
74AVC16245
The 74AVC16245 is a 16-bit transceiver featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions.
The 74AVC16245 features two output enable inputs (nOE)
for easy cascading and two send/receive inputs (nDIR) for
direction control. Input nOE controls the outputs so that the
buses are effectively isolated. This device can be used as
two 8-bit transceivers or one 16-bit transceiver.
This product is designed to have an extremely fast
propagation delay and a minimum amount of power
consumption.
To ensure the high-impedance output state during
power-up or power-down, input nOE should be tied to V
CC
through a pull-up resistor (live insertion).
A DCO circuitry is implemented to support termination line
drive during transient (see Figs 1 and 2).
MNA506
handbook, halfpage
0
MNA507
handbook, halfpage
300
I OH
(mA)
1.8 V
−100
I OL
(mA)
200
2.5 V
2.5 V
3.3 V
−200
100
1.8 V
3.3 V
−300
0
0
1
2
3
VOH (V)
4
0
1
2
3
VOL (V)
4
Fig.1 Output current as function of output voltage.
Fig.2 Output current as function of output voltage.
1999 Nov 15
2
Philips Semiconductors
Product specification
16-bit transceiver with direction pin; 3-state
(3.6 V tolerant)
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.0 ns; C
L
= 30 pF.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay nA
n
to nB
n
;
nB
n
to nA
n
CONDITIONS
V
CC
= 1.2 V
V
CC
= 1.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
C
I
C
PD
input capacitance
power dissipation capacitance per buffer notes 1 and 2
outputs enabled
outputs disabled
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
.
FUNCTION TABLE
See note 1.
INPUTS
nOE
L
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
nDIR
L
H
X
nA
n
A=B
inputs
Z
42
2
2.8
1.8
1.8
1.3
1.1
5.0
74AVC16245
TYP.
ns
ns
ns
ns
ns
pF
pF
pF
UNIT
INPUTS/OUTPUTS
nB
n
inputs
B=A
Z
1999 Nov 15
3
Philips Semiconductors
Product specification
16-bit transceiver with direction pin; 3-state
(3.6 V tolerant)
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
74AVC16245DGG
PINNING
PIN
1
2, 3, 5, 6, 8, 9, 11 and 12
4, 10, 15, 21, 28, 34, 39 and 45
7, 18, 31 and 42
13, 14, 16, 17, 19, 20, 22 and 23
24
25
26, 27, 29, 30, 32, 33, 35 and 36
37, 38, 40, 41, 43, 44, 46 and 47
48
SYMBOL
1DIR
1B
0
to 1B
7
GND
V
CC
2B
0
to 2B
7
2DIR
2OE
2A
7
to 2A
0
1A
7
to 1A
0
1OE
direction control
data inputs/outputs
ground (0 V)
DC supply voltage
data inputs/outputs
direction control
−40
to +85
°C
PINS
48
PACKAGE
TSSOP
74AVC16245
MATERIAL
plastic
CODE
SOT362-1
DESCRIPTION
output enable input (active LOW)
data inputs/outputs
data inputs/outputs
output enable input (active LOW)
1999 Nov 15
4
Philips Semiconductors
Product specification
16-bit transceiver with direction pin; 3-state
(3.6 V tolerant)
74AVC16245
handbook, halfpage
1DIR
1B0
1B1
GND
1B2
1B3
VCC
1B4
1B5
1
2
3
4
5
6
7
8
9
48 1OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 VCC
41 1A4
40 1A5
39 GND
38 1A6
46
1A1
44
1A2
43
1A3
41
1A4
40
1A5
38
1A6
37
1A7
36
2A0
1A0
47
1
2
3
5
6
8
9
11
12
13
4
5
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2
1B0
48
1OE
1
1DIR
25
2OE
24
2DIR
G3
3EN1[BA]
3EN2[AB]
G6
6EN1[BA]
6EN2[AB]
GND 10
1B6 11
1B7 12
2B0 13
2B1 14
GND 15
2B2 16
2B3 17
VCC 18
2B4 19
2B5 20
GND 21
2B6 22
2B7 23
2DIR 24
MNA508
16245
37 1A7
36 2A0
35 2A1
34 GND
33 2A2
32 2A3
31 VCC
30 2A4
29 2A5
28 GND
27 2A6
26 2A7
25 2OE
2A1
2A2
2A3
2A4
2A5
2A6
2A7
35
33
32
30
29
27
26
14
16
17
19
20
22
23
2B1
2B2
2B3
2B4
2B5
2B6
2B7
MNA003
Fig.3 Pin configuration.
Fig.4 IEEE/IEC logic symbol.
1999 Nov 15
5
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