DISCONTINUED MAR 2009
TB62706BNG/BFG
TOSHIBA Bi- CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
TB62706BNG, TB62706BFG
16BIT SHIFT REGISTER, LATCHES & CONSTANT CURRENT DRIVERS
The TB62706BNG, TB62706BFG are specifically designed for LED
and LED DISPLAY constant current drivers.
This constant current output circuits are able to set up external
resistor (I
OUT
= 5~90 mA). (Note)
These devices are monolithic integrated circuit designed to be used
together with Bi- CMOS process.
The devices consist of 16bit shift register, latch, AND- GATE and
Constant Current Drivers.
These products are Pb free.
TB62706BNG
FEATURES
l
Constant Current Output
: Can set up all output current with
one resister for 5 to 90 mA.
TB62706BFG
l
Maximum Clock Frequency : f
CLK
= 15 (MHz) (Cascade
Connected Operate, T
opr
= 25°C)
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5 V C- MOS Compatible Input
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Package : SDIP24- P- 300- 1.78 (TB62706BNG)
SSOP24- P- 300- 1.00B
OUTPUT- GND
VOLTAGE
=0.4 V
=0.7 V
CURRENT
MATCHING
±6.0%
±6.0%
(TB62706BFG)
OUTPUT
CURRENT
5~40 mA
5~90 mA
l
Constant Output Current Matching:
Weight
SDIP24-P-300-1.78 : 1.22 g (typ.)
SSOP24-P-300-1.00B : 0.32 g (typ.)
PIN CONNECTION
(Top view)
Company Headquarters
3 Northway Lane North
Latham,
New York
12110
Toll Free: 800.984.5337
Fax:
518.785.4725
Web: www.marktechopto.com | Email: info@arktechopto.com
TB62706BNG/BFG
BLOCK DIAGRAM
TIMING DIAGRAM
Note:
Latches are level sensitive, not rising edges sensitive and not syncronus CLOCK.
Input of LATCH- terminal to H Level, data passes latches, and input to L level, data hold latches.
Input of ENABLE- terminal to H level, all output (OUT0~15) do off.
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2004-06-24
TB62706BNG/BFG
TERMINAL DISCRIPTION
PIN No.
1
2
3
4
5~20
21
22
23
24
PIN NAME
GND
SERIAL- IN
CLOCK
LATCH
OUT0 ~ 15
ENABLE
FUNCTION
GND terminal for control logic.
Input terminal of a serial- data for shift- register.
Input terminal of a clock for data shift to up- edge.
Input terminal of a data strobe. Latches passes data with “H” level input of
LATCH
- terminal, and hold data with "L" level input.
Output terminals.
Input terminal of output enable. All outputs (OUT0~15) do off with “H” level input of
ENABLE
- terminal, and do on with "L" level input.
Output terminal of a serial- data for next SERIAL- IN terminal.
Input terminal of connects with a resister for to set up all output current.
5 V Supply voltage terminal.
SERIAL- OUT
R- EXT
V
DD
TRUTH TABLE
CLOCK
UP
UP
UP
DOWN
DOWN
LATCH
ENABLE
SERIAL- IN
D
n
D
n+1
D
n+2
D
n+3
D
n+3
OUT0
···
OUT7
···
OUT15
SERIAL- OUT
D
n- 15
D
n- 14
D
n- 13
D
n- 13
D
n- 13
H
L
H
X
X
L
L
L
L
H
D
n
··· D
n- 7
··· D
n- 15
No change
D
n+2
··· D
n- 5
··· D
n- 13
D
n+2
··· D
n- 5
··· D
n- 13
Off
Note:
OUT0 ~ 15
= on in case of D
n
= H level and
OUT0 ~ 15
= off in case of D
n
= L level.
A resistor is connected with R- EXT and GND accompanied with outside, and it is necessary that a correct power
supply voltage is supplied.
EQUIVALENT CIRCUIT OF INPUTS AND OUTPUTS
1.
ENABLE
terminal
2.
LATCH
terminal
3. CLOCK, SERIAL- IN terminal
4. SERIAL- OUT terminal
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TB62706BNG/BFG
MAXIMUM RATINGS
(Ta = 25°C)
CHARACTERISTIC
Supply Voltage
Input Voltage
Output Current
Output Voltage
Clock Frequency
GND Terminal Current
Power Dissipation
SYMBOL
V
DD
V
IN
I
OUT
V
OUT
f
CK
I
GND
P
D
RATING
0~7.0
- 0.4~V
DD
+ 0.4
90
- 0.5~17.0
15
1440
1.78 (BNG- type : ON PCB, Ta = 25°C )
1.00 (BFG- type : ON PCB, Ta = 25°C )
BNG : 70 (BN- type : ON PCB)
BFG : 120 (BF- type : ON PCB)
- 40~85
- 55~150
°C
°C
°C / W
UNIT
V
V
mA
V
MHz
mA
W
Tharmal Resistance
Operating Temperature
Storage Temperature
R
th (j- a)
T
opr
T
stg
Note:
BN- type :Ambient temperature delated above 25°C in the proportion of 14.2 mW / °C
BF- type : Ambient temperature delated above 25°C in the proportion of 8.3 mW / °C
RECOMMENDED OPERATING CONDITION
(Ta = - 40~85°C unless otherwise noted)
CHARACTERISTIC
Supply Voltage
Output Voltage
SYMBOL
V
DD
V
OUT
I
O
Output Current
I
OH
I
OL
V
IH
Input Voltage
V
IL
LATCH
Pulse Width
t
w LAT
CONDITION
–
–
OUTn, DC 1 circuit
SERIAL- OUT
SERIAL- OUT
–
–
MIN
4.5
–
5
–
–
0.7
V
DD
- 0.3
100
50
4500
TYP.
5.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MAX
5.5
15.0
88
1.0
- 1.0
V
DD
+0.3
0.3
V
DD
–
–
–
–
–
–
–
10.0
0.92
0.50
UNIT
V
V
mA
V
ns
ns
ns
ns
ns
ns
ns
MHz
W
CLOCK Pulse Width
ENABLE
Pulse Width
t
w CLK
t
w EN
Set- Up Time for DATA
Hold Time for DATA
Set- Up Time for
LATCH
Hold Time for
LATCH
Clock Frequency
Power Dissipation
t
setup (D)
t
hold (D)
t
setup (L)
t
hold (L)
f
CLK
P
D
V
DD
= 4.5~5.5 V
60
20
100
60
Cascade operation
Ta = 85°C (BNG- type)
Ta = 85°C (BFG- type)
–
–
–
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2004-06-24
嵌入式系统
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