HI-8783, HI-8784, HI-8785
January 2001
DESCRIPTION
The HI-8783, HI-8784, and HI-8785 are system compo-
nents for interfacing 8 bit parallel data to an ARINC 429
bus. The HI-8783 is a logic device only and requires a sep-
arate line driver circuit, such as the HI-8382 or HI-8585.
The HI-8784 and HI-8785 combine logic and line driver on
one chip. The HI-8784 has an output resistance of 37.5
ohms, and the HI-8785 has an output resistance of 10
ohms to facilitate external lightning protection cicuitry. The
technology is analog/digital CMOS.
The HI-8783 is available in a 22 pin DIP format as a second
source replacement for the Micrel / California Devices
DLS-111BV.
The products offer high speed data bus data transactions
to a buffer register. After loading 4 bytes, data is automati-
cally transferred and transmitted. The data rate is equal to
the clock rate. Parity can be enabled in the 32nd bit. Reset
is used to initialize the logic upon startup. Word gaps are
transmitted automatically.
The HI-8784 and HI-8785 require +/- 10 volt supplies in ad-
dition to the 5 volt supply.
PIN CONFIGURATIONS
VCC
561 SYNC
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
10
20
19
18
561 DATA
DATA ZERO
DATA ONE
PARITY ENB
XMT READY
XMIT CLK
RESET
WRITE
A0
GND
HI-8783PSI
&
HI-8783PST
17
16
15
14
13
12
11
20-Pin Plastic SOIC - WB package
FEATURES
l
VCC
561 SYNC
D0
D1
D2
D3
D4
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
V+
561 DATA
TXBOUT
TXAOUT
V-
PARITY ENB
XMT READY
XMIT CLK
RESET
WRITE
SLP1.5
A0
Automatically converts 8 bit parallel data
to ARINC 429 or 561 data
High speed data bus interface
On-chip line driver option
SOIC packages available
Military processing options
l
l
l
l
HI-8784PSI
HI-8784PST
HI-8785PSI
&
HI-8785PST
21
20
19
18
17
16
15
14
13
D5
D6
NC
D7
GND
24-Pin Plastic SOIC - WB package
(See page 7 for additional pin configurations)
(DS8783 Rev. B)
HOLT INTEGRATED CIRCUITS
1
01/01
HI-8783, HI-8784, HI-8785
PIN DESCRIPTIONS
PIN
PIN
PIN
HI-8783 HI-8783 HI-8784
(20-pin) (22-pin) HI-8785
1
2
3-10
11
12
-
13
14
15
16
17
-
18
19
-
-
20
-
22
1
2-8,10
11
12
-
14
15
16
17
18
-
19
20
-
-
21
-
1
2
3-9,11
12
13
14
15
16
17
18
19
20
-
-
21
22
23
24
SYMBOL
FUNCTION
DESCRIPTION
VCC
561 SYNC
Dn
GND
A0
SLP1.5
WRITE
RESET
XMIT CLK
XMT RDY
V-
DATA ONE
TXAOUT
TXBOUT
561 DATA
V+
power supply +5 volt rail,
digital output
digital inputs
digital input
digital input
digital input
digital input
digital input
digital output
ARINC 561 Sync signal
Parallel 8 bit Data Input
Byte address, A0=1 for 1st byte, A0=0 for 2nd, 3rd & 4th bytes
Selects the slope of the line driver. High = 1.5us
Write strobe, loads data on rising edge
Registers and sequencing logic initialized when low
Clock input for the transmitter
Goes high if the buffer register is empty
When high the 32nd bit output is odd parity
Goes high for each ARINC bit output that is a “one”
Goes high for each ARINC bit output that is a “zero”
power supply Ground
PARITY ENB digital input
digital output
power supply -10 volt rail
DATA ZERO digital output
analog output Line driver ouptut - A side
analog output Line driver output - B side
digital output
Serial output for ARINC 561 data
power supply +10 volt rail
FUNCTIONAL DESCRIPTION
The HI-8783 is a parallel to serial converter, which when
loaded with four eight bit parallel bytes, outputs the data as
a 32 bit serial word. Timing circuitry inserts a 4 bit gap at the
end of each 32 bit word. An input buffer register allows load
operations to take place while the previously loaded word
is being transmitted.
If the PARITY ENB pin is high, the 32nd bit will be a parity
bit, inserted so as to make the 32 bit word have odd parity. If
the PARITY ENB pin is low, the 32nd bit will be the D7 bit of
the 4th byte.
Outputs are provided for both ARINC 429/575 (DATA ONE
and DATA ZERO pins), and ARINC 561 (561 DATA and
561 SYNC pins) type data.
A low signal applied to the RESET pin resets the HI-8783’s
internal logic so that spurious transmission does not take
place during power-up. The registers are cleared so that a
continuous gap will be transmitted until the first word is
loaded into the transmitter.
Input data can be loaded when the XMT RDY signal is
high, which indicates the input buffer register is empty. The
first 8 bit byte is the label byte and is loaded with the A0 in-
put high, which initializes the internal byte counter. The re-
maining three bytes are loaded with A0 in the low state.
Each 8 bit byte is loaded into the input buffer register by a
low pulse on the WRITE input. (See figure 1). After the
fourth byte is loaded, the XMT RDY output goes low. The
contents of the input buffer register are transferred to the
output register during the fourth bit period of the gap. If the
fourth gap bit period of the previous word has already been
transmitted, the contents of the input buffer register will be
transferred to the output shift register during the first bit pe-
riod after the loading of the fourth byte, and the XMT RDY
output goes high.
After the output shift register is loaded, the data is shifted
out to the output logic in the order shown in figure 2.
The 561 SYNC output pulses low when the XMT CLK is low
during the 8th bit of the ARINC transmission.
The XMIT CLK is the same as the data rate.
HOLT INTEGRATED CIRCUITS
2
HI-8783, HI-8784, HI-8785
XMIT CLK
XMT RDY
WRITE
A0
byte
counter
status &
control
logic
SLP1.5
TXAOUT
line
driver
word gap
counter
TXBOUT
HI-8784, HI8785
DATA
BUS
8 to 32 bit
mux
8
32
32 bit
buffer
register
32
32 bit
shift
register
bit
counter
DATA ONE
DATA ZERO
output
logic
HI-8783
561 SYNC
561 DATA
PARITY ENB
Figure 1. Block Diagram
FUNCTIONAL DESCRIPTION (Cont.)
The HI-8784 and HI-8785 have the same digital logic func-
tion as the HI-8783, but include an on-chip line driver de-
signed to directly drive the ARINC 429 bus. The two ARINC
outputs (TXAOUT and TXBOUT) provide a differential volt-
age to produce a +10 volt One, a -10 volt Zero, and a 0 volt
Null. The slope of the ARINC outputs is controlled by the
SLP1.5 pin. If SLP1.5 is high, the output rise and fall time is
nominally 1.5us. If SLP1.5 is set low, the rise and fall times
are 10us. DATA ONE and DATA ZERO outputs are not pro-
vided for the HI-8784 and HI-8785.
The HI-8784 has 37.5 ohms in series with each line driver
output. The HI-8785 has 10.0 ohms in series. The HI-8785
is for applications where external series resistance is
needed, typically for lightning protection devices.
A0
1
0
0
0
Byte
Byte 1
Byte 2
Byte 3
Byte 4
Data Bus
D0 - D7
D0 - D7
D0 - D7
D0 - D7
ARINC Bits
ARINC 1 - ARINC 8
ARINC 9 - ARINC 16
ARINC 17 - ARINC 24
ARINC 25 - ARINC 32
Figure 2. Order of transmitted bytes
HOLT INTEGRATED CIRCUITS
3
HI-8783, HI-8784, HI-8785
35
XMIT CLK
36
1
2
3
4
5
31
32
33
34
35
36
DATA ONE
DATA ZERO
561 DATA
561 SYNC
LOW DURING CLK 8
XMT CLK
t phlx
t plhx
DATA ONE
t phlx
DATA ZERO
t rx
90%
10%
90%
10%
10%
t plhx
5V
0V
5V
0V
t rx
10V
0V
-10V
t fx
t fx
HOLT INTEGRATED CIRCUITS
4
HI-8783, HI-8784, HI-8785
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to Ground
Supply voltages
V+.................................................12.5V
V-.................................................-12.5V
VCC.................................................. 7V
DC current per input pin................ +10ma
Power dissipation at 25°
plastic DIL............1.0W, derate 10mW/°C
ceramic DIL..........0.5W, derate 7mW/°C
Solder Temperature ........275°C for 10 sec
Storage Temperature........-65°C to +150°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltages
V+.......................................+10V... ±5%
V-........................................ -10V... ±5%
VCC....................................... 5V... ±5%
Temperature Range
Industrial Screening.........-40°C to +85°C
Hi-Temp Screening........-55°C to +125°C
Military Screening..........-55°C to +125°C
NOTE:
Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to the
device. These are stress ratings only. Operation at
the limits is not recommended.
VCC = 5.0V, V
SS
= 0V, T
A
= Operating Temperature Range (unless otherwise specified).
PARAMETER
Operating Voltage
Min. Input Voltage
Max. Input Voltage
Min. Input Current
Max. Input Current
Min. Output Voltage
Max. Output Voltage
(HI)
(LO)
(HI)
(LO)
(HI)
(LO)
SYMBOL
V
CC
V
IH
V
IL
I
IH
I
IL
V
OH
V
IH
I
CC
C
IN
CONDITION
MIN
4.75
2.0
TYP
5
1.4
1.4
MAX
5.25
UNITS
V
V
0.8
1
V
µA
µA
V
V
IH
= 4.9V
V
IL
= 0.1V
I
OUT
= -1.6mA
I
OUT
= 1.6mA
f = 100khz
Not tested
0.8
-1
2.7
0.4
2.8
20
V
mA
pF
Operating Current Drain
Input Capacitance
VCC = 5.0V, V
SS
= 0V, V+ = 10V, V- = -10V, T
A
= Operating Temperature Range (unless otherwise specified).
PARAMETER
Operating Voltage
Operating Voltage
Operating Current Drain (V+)
Operating Current Drain (V-)
Line Driver Output Levels (Ref. To GND)
ONE
NULL
ZERO
Line Driver Output Levels (Differential)
ONE
NULL
ZERO
Minimum Short Circuit Sink or Source Current
SYMBOL
V+
V-
I
DD
I
EE
CONDITION
MIN
9.5
-9.5
TYP
10
-10
6
MAX
10.5
10.5
20
UNITS
V
V
mA
mA
no load, f = 100khz
no load, f = 100khz
-20
-6
no load, VCC = 5.0V
“
“
4.5
-0.25
-5.55
5.0
0
-5.0
5.5
0.25
-4.5
V
V
V
no load, VCC = 5.0V
“
“
I
OUT
momentary magnitude
9.0
-0.5
-11.0
80
10.0
0
-10.0
11.0
0.5
-9.0
V
V
V
mA
HOLT INTEGRATED CIRCUITS
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
