Preliminary Spec.
MITSUBISHI LSIs
MH32V725BST -5, -6
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH32V725BST is 33554432-word x 72-bit dynamic
ram stacked structural module. This consist of thirty-six
industry standard 16M x 4 dynamic RAMs in TSOP and
two industry standard input buffer in TSSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
PIN CONFIGURATION
85pin
94pin
1pin
10pin
11pin
FEATURES
Type name
MH32V725BST-5
MH32V725BST-6
/RAS
/CAS Address /OE
access access access access
time
time
time
time
Cycle
time
Power
dissipation
(typ.W)
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
95pin
50
60
19
21
30
35
19
21
84
104
12.8
11
Utilizes industry standard 16M x 4 RAMs SOJ and industry
standard input buffer in TSSOP
168-pin (84-pin dual dual in-line package)
Single 3.3V(± 0.3V) supply operation
Low stand-by power dissipation . . . . . . . . . . 135.7mW(Max)
Low operation power dissipation
MH32V725BST -5 . . . . . . . . . . . . . . . . . . 14.96W(Max)
MH32V725BST -6 . . . . . . . . . . . . . . . . . . 13.66W(Max)
All input are directly LVTTL compatible
All output are three-state and directry LVTTL compatible
Includes(0.22 uF x 38) decoupling capacitors
4096 refresh cycle every 64ms (CBR Ref)
8192 refresh cycle every 64ms (RAS Only Ref,Normal R/W)
Hyper-page mpde,Read-modify-write,/CAS before /RAS refresh,
Hidden refresh capabilities
JEDEC standard pin configration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads
124pin
BACK SIDE
125pin
40pin
FRONT SIDE
41pin
APPLICATION
Main memory unit for computers , Microcomputer memory
168pin
84pin
PD&ID TABLE
-5
-6
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered
1
MIT - DS - 0237-0.0
MITSUBISHI
ELECTRIC
27/Jul./1998
Preliminary Spec.
MITSUBISHI LSIs
MH32V725BST -5, -6
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
PIN CONFIGURATION
Pin No.
Pin Name
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
DQ16
DQ17
Vss
Reserved
Reserved
Vcc
/WE0
/CAS0
Reserved
/RAS0
/OE0
Vss
A0
A2
A4
A6
A8
A10
A12
Vcc
RFU
RFU
Pin No.
Pin Name
Vss
/OE2
/RAS2
/CAS4
Reserved
/WE2
Vcc
Reserved
Reserved
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vcc
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
Vss
DQ28
DQ29
DQ30
DQ31
Vcc
DQ32
DQ33
DQ34
DQ35
Vss
PD1
PD3
PD5
PD7
ID0
Vcc
Pin No.
Pin Name
Vss
DQ36
DQ37
DQ38
DQ39
Vcc
DQ40
DQ41
DQ42
DQ43
DQ44
Vss
DQ45
DQ46
DQ47
DQ48
DQ49
Vcc
DQ50
DQ51
DQ52
DQ53
Vss
Reserved
Reserved
Vcc
RFU
/CAS1
Reserved
/RAS1
RFU
Vss
A1
A3
A5
A7
A9
A11
Reserved
Vcc
RFU
B0
Pin No.
Pin Name
Vss
RFU
/RAS3
/CAS5
Reserved
/PDE
Vcc
Reserved
Reserved
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ62
DQ63
Vss
DQ64
DQ65
DQ66
DQ67
Vcc
DQ68
DQ69
DQ70
DQ71
Vss
PD2
PD4
PD6
PD8
ID1
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Reserved: Reserved use
RFU: Reserved for future use
2
MIT - DS - 0237-0.0
MITSUBISHI
ELECTRIC
27/Jul./1998
Preliminary Spec.
MITSUBISHI LSIs
MH32V725BST -5, -6
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
BLOCK DIAGRAM
/RAS0
/CAS0
/RAS1
/CAS1
/WE0
/OE0
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/RAS2
/CAS4
/RAS3
/CAS5
/WE2
/OE2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
/OE /W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
D0
D18
D9
D27
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
DQ65
DQ66
DQ67
DQ68
DQ69
DQ70
DQ71
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE /W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
D1
D19
D10
D28
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE /W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
D2
D20
D11
D29
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE /W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
D3
D21
D12
D30
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE /W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
D4
D22
D13
D31
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE /W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
D5
D23
D14
D32
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE /W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
D6
D24
D15
D33
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE /W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
D7
D25
D16
D34
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/OE /W
/CAS
/RAS
DQ1
~DQ4
/OE
/W
/CAS
/RAS
DQ1
~DQ4
D8
D26
D17
D35
D : M5M467405BTP
D0 - D8
D18 - D26
D9 - D17
D27 - D35
D0 - D35
PIN NAME
/RAS
/CAS
/WE
/OE
A, B
DQ
Vcc
Vss
FUNCTION
ROW ADDRESS STROBE INPUT
COLUMN ADDRESS STROBE INPUT
WRITE CONTROL INPUT
OUTPUT ENABLE INPUT
ADDRESS INPUT
DATA I/O
POWER SUPPLY
GROUND
A0
B0
A1 - A12
Vcc
Vss
C
1
. - C
38
..
D0 - D35
& INPUT BUFFER
3
MIT - DS - 0237-0.0
MITSUBISHI
ELECTRIC
27/Jul./1998
Preliminary Spec.
MITSUBISHI LSIs
MH32V725BST -5, -6
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
FUNCTION
The MH32V725BST provide, in addition to normal read,
write, and read-modify-write operations,
a number of other functions, e.g., hyper page mode, /CAS
before /RAS refresh, and delayed-write. The input conditions
for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Operation
/RAS
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
Hidden refresh
/CAS before /RAS refresh
Standby
ACT
ACT
ACT
ACT
ACT
ACT
NAC
/CAS
ACT
ACT
ACT
ACT
ACT
ACT
DNC
/W
NAC
ACT
ACT
ACT
DNC
NAC
DNC
/OE
ACT
DNC
DNC
ACT
ACT
DNC
DNC
Row
address
APD
APD
APD
APD
DNC
DNC
DNC
Column
address
APD
APD
APD
APD
DNC
DNC
DNC
Input/Output
Refresh
Input
OPN
VLD
VLD
VLD
OPN
DNC
DNC
Output
VLD
OPN
IVD
VLD
VLD
OPN
OPN
NO
NO
NO
NO
YES
YES
NO
Hyper page mode
identical
Remark
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
4
MIT - DS - 0237-0.0
MITSUBISHI
ELECTRIC
27/Jul./1998
Preliminary Spec.
MITSUBISHI LSIs
MH32V725BST -5, -6
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
IO
Pd
Topr
Tstg
Parameter
Supply voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to Vss
Ta=25°C
Ratings
-0.5~4.6
50
38
0~70
-40~125
Unit
V
mA
W
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage
Min
3.0
0
2.0
-0.3
(Ta=0~70°C, unless otherwise noted) (Note 1)
Limits
Nom
3.3
0
Max
3.6
0
Vcc+0.3
Unit
V
V
V
V
0.8
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol
VOH
VOL
IOZ
II
I I (RAS)
ICC1 (AV)
Parameter
High-level output voltage
Low-level output voltage
Off-state output current
Input current (except /RAS)
Input current (/RAS)
Average supply
current
from Vcc operating
(Ta=0~70°C, Vcc=3.3V +/- 0.3V, Vss=0V, unless otherwise noted) (Note 2)
Test conditions
IOH=-2.0mA
IOL=2.0mA
Q floating 0V
0V
0V
Min
2.4
0
Vcc
-20
-1
-90
Limits
Typ
Max
Vcc
0.4
20
1
90
1825
1645
43
25
1825
1645
4687
4327
Unit
V
V
uA
uA
uA
mA
VII
VII
VOUT
-5
(Note 3,4,5)
-6
/RAS, /CAS cycling
tRC=tWC=min.
output open
/RAS=/CAS =VIH, output open
/RAS=/CAS Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.
output open
IIV
/CAS before /RAS refresh cycling
tRC=min.
output open
VII VII
VIN
VIN
VII VII
Vcc+0.3V, Other input pins=0V
Vcc+0.3V, Other input pins=0V
ICC2
Supply current from Vcc , stand-by
Average supply current
from Vcc
Hyper-Page-Mode
mA
mA
-5
(Note 3,4,5)
ICC4(AV)
-6
-5
-6
ICC6(AV)
Average supply current from Vcc
/CAS before /RAS refresh
mode
mA
(Note 3,5)
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of colmun address being changed once or less while /RAS=VIL and /CAS=VIH
CAPACITANCE
Symbol
(Ta = 0~70°C, Vcc = 3.3V +/- 0.3V, Vss = 0V, unless otherwise noted)
Parameter
Test conditions
VI=Vss
f=1MHZ
Vi=25mVrms
Min
Limits
Typ
CI (/RAS) Input capacitance, /RAS input
CI
Input capacitance, except /RAS input
C(DQ)
Input/Output capacitance,DATA
Max
78
21
29
Unit
pF
pF
pF
5
MIT - DS - 0237-0.0
MITSUBISHI
ELECTRIC
27/Jul./1998
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