Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
Utilizes industry standard 16M x 16 Synchronous
DRAMs TSOP and industry standard EEPROM in
TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH32S64PFJ is 33554432 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 16Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
FEATURES
Frequency
-6,-6L
-7,-7L
133MHz
100MHz
CLK Access Time
(Component SDRAM)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
8192 refresh cycle /64ms
LVTTL Interface
5.4ns(CL=3)
6.0ns(CL=2)
PC133/100 Compliant
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
(Back)
1
2
143
144
MIT-DS-0337-0.2
MITSUBISHI
ELECTRIC
( 1 / 55 )
26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
PIN CONFIGURATION
PIN
Number
Front side
Pin Name
PIN
Number
Back side
Pin Name
PIN
Number
Front side
Pin Name
PIN
Number
Back side
Pin Name
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
Vss
DQMB0
DQMB1
Vcc
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ12
DQ13
DQ14
DQ15
Vss
Reserved
Reserved
CLK0
Vcc
/RAS
/WE
/S0
/S1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
DQMB4
DQMB5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
DQ45
DQ46
DQ47
Vss
Reserved
Reserved
CKE0
Vcc
/CAS
CKE1
A12
A13
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Reserved
Vss
Reserved
Reserved
Vcc
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vcc
A6
A8
Vss
A9
A10
Vcc
DQMB2
DQMB3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
CLK1
Vss
Reserved
Reserved
Vcc
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
DQ54
DQ55
Vcc
A7
BA0
Vss
BA1
A11
Vcc
DQMB6
DQMB7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vcc
NC = No Connection
MIT-DS-0337-0.2
MITSUBISHI
ELECTRIC
( 2 / 55 )
26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Block Diagram
/S0
/S1
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQML /CS
DQML /CS
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQML /CS
DQML /CS
I/O 0
I/O 1 D0
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 0
I/O 1 D4
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DQMU
DQMU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
9
10
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
9
10
11
12
13
14
15
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
10Ω
DQML /CS
DQML /CS
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQML /CS
DQML /CS
I/O 0
I/O 1 D1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 0
I/O 1 D5
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1 D7
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DQMU
DQMU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
9
10
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
9
10
11
12
13
14
15
CLK0
CLK1
CKE0
CKE1
/RAS
/CAS
/WE
BA0,BA1,A<12:0>
Vcc
Vss
4loads
4loads
D0 - D3
D4 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
SERIAL PD
SCL
A0
A1
A2
SDA
MIT-DS-0337-0.2
MITSUBISHI
ELECTRIC
( 3 / 55 )
26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
-6
-7
-6
-7
SPD enrty data
128
256 Bytes
SDRAM
A0-A12
A0-A8
2BANK
x64
0
LVTTL
7.5ns
10ns
5.4ns
6ns
Non-PARITY
SPD DATA(hex)
80
08
04
0D
09
02
40
00
01
75
A0
54
60
00
82
10
00
01
8F
04
06
01
01
00
0E
A0
A0
60
60
00
00
14
0F
14
14
2D
32
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
self refresh(7.8125uS)
x16
N/A
1
1/2/4/8/Full page
4bank
2/3
0
0
non-buffered,non-registered
Precharge All,Auto precharge
-6
-7
-6
-7
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
CS# Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes:General
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
10ns
10ns
6ns
6ns
N/A
N/A
20ns
15ns
20ns
20ns
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25
26
27
28
29
30
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Precharge to Active Minimum
Row Active to Row Active Min.
RAS to CAS Delay Min
-6
-7
-6
-7
Active to Precharge Min
45ns
50ns
MIT-DS-0337-0.2
MITSUBISHI
ELECTRIC
( 4 / 55 )
26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31
32
33
Density of each bank on module
Command and Address signal input setup time
Command and Address signal input hold time
-6
-7
-6
-7
34
35
36-61
62
63
Data signal input setup time
Data signal input hold time
Superset Information (may be used in future)
SPD Revision
Checksum for bytes 0-62
-6
-7
-6
-7
128MByte
1.5ns
2ns
0.8ns
1ns
1.5ns
2ns
0.8ns
1ns
option
rev 1.2B
Check sum for -6
Check sum for -7
64-71
72
Manufactures Jedec ID code per JEP-108E
Manufacturing location
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
73-90
Manufactures Part Number
MH32S64PFJ-6
MH32S64PFJ-6L
MH32S64PFJ-7
MH32S64PFJ-7L
91-92
93-94
95-98
99-125
126
127
128+
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
Intel specification CAS# Latency support
Unused storage locations
-6,-7
20
15
20
08
10
15
20
08
10
00
12
BA
21
1CFFFFFFFFFFFFFF
01
02
03
04
4D48333253363450464A2D36202020202020
4D48333253363450464A2D364C2020202020
4D48333253363450464A2D37202020202020
4D48333253363450464A2D374C2020202020
PCB revision
year/week code
serial number
option
100MHz
CL=2/3,AP,CK0,1
open
rrrr
yyww
ssssssss
00
64
CF
00
The -6, -7 indicate also -6L, -7L.
MIT-DS-0337-0.2
MITSUBISHI
ELECTRIC
( 5 / 55 )
26.Apr.2001
FPGA/CPLD
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