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Regarding the change of names mentioned in the document, such as Mitsubishi
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Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Mitsubishi 32-bit RISC Single-chip Microcomputers
M32R Family M32R/ECU Series
32170
32174
G r o u p
User's Manual
http://www.infomicom.maec.co.jp/indexe.htm
Before using this material, please visit the above website to confirm that this is
the most current document available.
Rev. 2.1
Revision date: Jan. 16, 2003
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor prod-
ucts better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
•
•
•
•
•
These materials are intended as a reference to assist our customers in the selection of the
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Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
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How to read internal I/O register tables
➀
Bit Numbers: Each register is connected with an internal bus of 16-bit
wide, so the bit numbers of the registers located at even
addresses are D0-D7, and those at odd addresses are
D8-D15.
➁
State of Register at Reset: Represents the initial state of each register
immediately after reset with hexadecimal numbers
(undefined bits after reset are indicated each in column
➂.)
➂
At read:
... read enabled
? ... read disabled (read value invalid)
0 ... Read always as 0
1 ... Read always as 1
: Write enabled
∆
: Write enable conditionally
(include some conditions at write)
- : Write disabled (Written value invalid)
{
At write:
<Example of representation>
Not implemented
in the shaded portion.
1
D0
1
Abit
2
Bbit
3
Cbit
Registers represented with thick rectangles
are accessible only with halfwords or words
(not accessible with bytes).
4
2
D
0
1
Bit name
Not assigned.
Abit
(...................)
2
Bbit
(...................)
3
Cbit
(...................)
0: -----
1: -----
0: -----
1: -----
0: -----
1: -----
Function
<at reset: H'04>
R
0
W
3
4
Revision History
Rev. Date of
issue
Pages
0.1 Mar.17,00 —
2.1 Jan.16,03 Overall
P1-7
P1-10
P1-11
32170/32174 Group User's Manual
Contents of revision
Points
First edition issued
Description of the 32174 group added
M32174F4 and M32174F3 added to the internal flash memory and internal
RAM in Figure 1.2.1
Table 1.2.4 added
Note 1 in Figure 1.3.1 corrected
Incorrect) Operates with a 5 V power supply.
Correct) Operates with 3.3 V and 5 V power supplies.
M32174F4VWG and M32174F3VWG added to Figure 1.3.2
Note 1 corrected
Incorrect) Operates with a 5 V power supply.
Correct) Operates with 3.3 V and 5 V power supplies.
P1-12
P1-13
P1-19
P1-22
P2-14
P3-6
P3-7
P3-10
P3-11
P3-12
P5-7
P5-8
P5-20-
P5-21
P6-2
P6-3
P6-40
P6-45
P6-46
P6-50
Table 1.3.1, "Description of the 32170 Pin Function," corrected
M32174F4VFP and M32174F3VFP added to Figure 1.4.1
M32174F4VWG and M32174F3VWG added to Figure 1.4.2
Section 2.7, "Precautions on CPU," newly added
Address space of the M32174F4 added to Figure 3.1.4
Address space of the M32174F3 added to Figure 3.1.5
M32174F4 and M32174F3 added to Table 3.3.1
M32174F4 and M32174F3 added to Table 3.4.1
Internal RAM area/SFR (Special Function Register) area of the M32174F4
and M32174F3 added to Figure 3.4.3
Caution corrected
Caution corrected
Section 5.5.2, "Processing by Internal Peripheral I/O Interrupt by Handlers," aftered
Figure 5.5.2 altered
M32174F4 and M32174F3 added to Table 6.2.1
M32174F4 and M32174F3 added to Table 6.3.1
Figure 6.5.15 corrected
Bank configuration of the M32174F4 and M32174F3’s internal RAM added
to Figure 6.7.3
Precautions in Notes 3 through 5 added
M32174F4’s virtual-flash emulation area divided in units of 8 Kbytes added
to Figure 6.7.10
(1⁄4)