2001-5-14 Rev.1.0
Mitsubishi Microcomputers
32170 Group, 32174 Group
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Description
The M32170 and M32174 Group are 32-bit single chip RISC
microcomputers designed for use in general industrial and
household equipment.
These microcomputers contains a variety of peripheral
functions ranging from16-channel A-D converters to 64chan-
nel multifunction timers, 10-channel DMAs, 6-channel serial
I/Os, 1-channel real time debugger, 1-channel Full-CAN, and
JTAG (boundary scan facility).
With lower power consumption and low noise characteristics
also considered, these microcomputers are ideal for embed-
ded equipment applications.
64-channel multijunction timers (MJT)
Multifunction timers are incorporated that support various
purposes of use.
16-bit output related timers ....................................... 35ch
16-bit input/output related timers .............................. 10ch
16-bit input related timers ......................................... 11ch
32-bit input related timers .......................................... 8ch
• Flexible configuration is possible through interconnection
of timers.
• The internal DMAC and A-D converter can be started by a
timer.
Real-time Debugger
Features
M32R RISC CPU core
• Uses the M32R family RISC CPU core (Instruction set
common to all microcomputers in the M32R family)
• Five-stage pipelined processing
• Sixteen 32-bit general-purpose registers
• 16-bit/32-bit instructions implemented
• DSP function instructions (sum-of-products calculation
using 56-bit accumulator)
• Built-in flash memory
• Built-in flash programming boot program
• Built-in RAM
• PLL clock generating circuit ........... Built-in
×
4 PLL circuit
• Maximum operating frequency of the CPU clock
40MHz(when operating at -40 to +85
o
C)
32MHz(when operating at -40 to +125 C)
Table 1 32170 Group Name List by type
Type Name
M32170F6VFP
M32170F4VFP
M32170F3VFP
M32170F6VWG
M32170F4VWG
M32170F3VWG
RAM Size
40K bytes
32K bytes
32K bytes
40K bytes
32K bytes
32K bytes
ROM Size
768K bytes
512K bytes
384K bytes
768K bytes
512K bytes
384K bytes
Package
240QFP
240QFP
240QFP
255FBGA
255FBGA
255FBGA
o
• Includes dedicated clock-synchronized serial I/O that can
read and write the contents of the internal RAM independently
of the CPU.
• Can look up and update the data table in real time while the
program is running.
• Can generate a dedicated interrupt based on RTD commu-
nication.
Abundant internal peripheral functions
In addition to the timers and real-time debugger, the micro-
computer contains the following peripheral functions.
• DMAC .............................................................. 10 channels
• Two independent
A-D converter .............. (10-bit converter
×
16 channels)
×
2
• Serial I/O ............................................................ 6 channels
• Interrupt controller ........... 31 interrupt sources, 8 priority levels
• Wait controller
• Full CAN .............................................................. 1 channel
• JTAG (boundary scan function)
Designed to operate at high temperatures
To meet the need for use at high temperatures, the micro-
computer is designed to be able to operate in the temperature
range of -40 to +125
o
C when CPU clock operating
frequency = 32 MHz. When CPU clock operating frequency =
40 MHz, the microcomputer can be used in the temperature
range of -40 to +85
o
C.
Note: This does not guarantee continuous operation at
125
o
C. If you are considering use of the microcom
puter at 125
o
C, please consult Mitsubishi.
Note: 255FBGA is currently under development.
Table 2 32170 Group Name List by type
Type Name
M32174F4VFP
M32174F3VFP
M32174F4VWG
M32174F3VWG
RAM Size
40K bytes
40K bytes
40K bytes
40K bytes
ROM Size
512K bytes
384K bytes
512K bytes
384K bytes
Package
240QFP
240QFP
255FBGA
255FBGA
Applications
Automobile equipment control (e.g., Engine, ABS, AT), indus-
trial equipment system control, and high-function OA equip-
ment (e.g., PPC)
Note: 255FBGA is currently under development.
2001-5-14 Rev.1.0
Mitsubishi Microcomputers
32170 Group, 32174 Group
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Pin Assignment(top view)
P217/TO44
P216/TO43
P215/TO42
P214/TO41
P213/TO40
P212/TO39
P211/TO38
P210/TO37
VSS
VCCI
VDD
P102/TO10
P101/TO9
P100/TO8
P117/TO7
P116/TO6
P115/TO5
P114/TO4
P113/TO3
P112/TO2
P111/TO1
P110/TO0
VSS
VCCE
FP
MOD1
MOD0
RESET
P97/TO20
P96/TO19
P95/TO18
P94/TO17
P93/TO16
P77/RTDCLK
P76/RTDACK
P75/RTDRXD
P74/RTDTXD
P73/ HACK
P72/ HREQ
P71/WAIT
P70/BCLK/WR
VCCE
VSS
VCCI
P67/ADTRG
P66/SCLKI5/SCLKO5
P65/SCLKI4/SCLKO4
P64/SBI
P63
P62
P61
VSS
FVCC
VSS
VCCI
P203/RXD5
P202/TXD5
P201/RXD4
P200/TXD4
P87/SCLKI1/SCLKO1
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
JTMS
JTCK
JTRST
JTDO
JTDI
P103/TO11
P104/TO12
P105/TO13
P106/TO14
P107/TO15
P124/TCLK0
P125/TCLK1
P126/TCLK2
P127/TCLK3
VCCI
VSS
P130/TIN16
P131/TIN17
P132/TIN18
P133/TIN19
P134/TIN20
P135/TIN21
P136/TIN22
P137/TIN23
VCCE
VSS
P140/TIN8
P141/TIN9
P142/TIN10
P143/TIN11
P144/TIN12
P145/TIN13
P146/TIN14
P147/TIN15
P150/TIN0
P151/TIN1
P152/TIN2
P153/TIN3
P154/TIN4
P155/TIN5
P156/TIN6
P157/TIN7
P41/BLW/BLE
P42/BHW/BHE
VCCI
VSS
VREF1
AVCC1
AD1IN0
AD1IN1
AD1IN2
AD1IN3
AD1IN4
AD1IN5
AD1IN6
AD1IN7
AD1IN8
AD1IN9
AD1IN10
AD1IN11
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
M32170F3VFP
M32170F4VFP
M32170F6VFP
M32174F3VFP
M32174F4VFP
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P86/RXD1
P85/TXD1
P84/SCLKI0/SCLKO0
P83/RXD0
P82/TXD0
VSS
VCCE
P177/RXD3
P176/TXD3
P175/RXD2
P174/TXD2
P173/TIN25
P172/TIN24
P167/TO28
P166/TO27
P165/TO26
P164/TO25
P163/TO24
P162/TO23
P161/TO22
P160/TO21
VSS
VCCI
P197/TIN33
P196/TIN32
P195/TIN31
P194/TIN30
P193/TIN29
P192/TIN28
P191/TIN27
P190/TIN26
P187/TO36
P186/TO35
P185/TO34
P184/TO33
P183/TO32
P182/TO31
P181/TO30
P180/TO29
VSS
VCCE
AVSS0
AD0IN15
AD0IN14
AD0IN13
AD0IN12
AD0IN11
AD0IN10
AD0IN9
AD0IN8
AD0IN7
AD0IN6
AD0IN5
AD0IN4
AD0IN3
AD0IN2
AD0IN1
AD0IN0
AVCC0
VREF0
Note: Use caution when using these pins because they nave a debug event function.
Figure 1 Pin Layout Diagram of the 240QFP
2
AD1IN12
AD1IN13
AD1IN14
AD1IN15
AVSS1
P43/RD
P44/CS0
P45/CS1
P46/A13
P47/A14
P220/CTX
P221/CRX
P222
P223
(Note) P224/A11
(Note) P225/A12
VSS
OSC-VSS
XIN
XOUT
OSC-VCC
VSS
VCNT
VSS
P30/A15
P31/A16
P32/A17
P33/A18
P34/A19
P35/A20
P36/A21
P37/A22
P20/A23
P21/A24
P22/A25
P23/A26
VCCE
VSS
P24/A27
P25/A28
P26/A29
P27/A30
P00/DB0
P01/DB1
P02/DB2
P03/DB3
P04/DB4
P05/DB5
P06/DB6
P07/DB7
VCCE
VSS
P10/DB8
P11/DB9
P12/DB10
P13/DB11
P14/DB12
P15/DB13
P16/DB14
P17/DB15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Package 240P6Y-A
2001-5-14 Rev.1.0
Mitsubishi Microcomputers
32170 Group, 32174 Group
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Pin Assignment(top view)
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JTMS
P216
/TO43
P217
/TO44
P214
/TO41
P215
/TO42
P213
/TO40
JTDO
P210
/TO37
P211
/TO38
P212
/TO39
VSS
P102
/TO10
P116 TRDATA
/TO6
6
P117 TRDATA
/TO7
7
P100
/TO8
P115
/TO5
P112
/TO2
P113
/TO3
VCCE
RESET
P96
P77/
P73
/TO19 RTDCLK /HACK
P95
P76/
P72
/TO18 RTDACK /HREQ
P94
P75/
P71
/TO17 RTDRXD /WAIT
VCCE
P66
/SCLK5
P65
/SCLK4
P64
/SBI
P63
P62
VSS
P202
/TXD5
P200
/TXD4
P201 TRDATA
/RXD4
3
TRDATA
1
JTCK
VDD
VSS
MOD0
VSS
P61
VCCI
N.C
JEVENT
0
JDBI
VCCI
P114 TRDATA
/TO4
4
TRDATA
5
P111
/TO1
P110
/TO0
FP
MOD1
VCCI
VSS
P203
/RXD5
P83
/RXD0
P177
/RXD3
P173
/TIN25
P165
/TO26
P161
/TO22
P87 TRDATA TRDATA
2
0
/SCLK1
P84
/SCLK0
P86
/RXD1
P82
/TXD0
P176
/TXD3
P172
/TIN24
P164
/TO25
P160
/TO21
P196
/TIN32
P190
/TIN26
P184
/TO33
P180
/TO29
P85
/TXD1
JEVENT JTRST
1
P104
/TO12
P124
/TCLK0
P103
/TO11
P107
/TO15
P127
/TCLK3
P131
/TIN17
P135
/TIN21
P101
/TO9
P97
/TO20
P70
P93
P74/
P67
/TO16 RTDTXD /BCLK /ADTRG
FVCC
P105
/TO13
P125
/TCLK1
JTDI
VCCE
VSS
P106
/TO14
P126
/TCLK2
P130
/TIN16
P134
/TIN20
P174
/TXD2
P166
/TO27
P162
/TO23
P175
/RXD2
P167
/TO28
P163
/TO24
VCCI
P132
/TIN18
P136
/TIN22
P140
/TIN8
P144
/TIN12
P150
/TIN0
P154
/TIN4
P41
/BLW
VSS
P133
/TIN19
P137
/TIN23
P141
/TIN9
P143
/TIN11
P147
/TIN15
P153
/TIN3
P157
/TIN7
VSS
VCCE
P145
/TIN13
P151
/TIN1
P155
/TIN5
P42
/BHW
P142
/TIN10
P146
/TIN14
P152
/TIN2
P156
/TIN6
M32170F3VWG
M32170F4VWG
M32170F6VWG
M32174F3VWG
M32174F4VWG
P197
/TIN33
P193
/TIN29
P187
/TO36
P183
/TO32
VCCI
VSS
P194
/TIN30
P192
/TIN28
P186
/TO35
P182
/TO31
P195
/TIN31
P191
/TIN27
P185
/TO34
P181
/TO30
VSS
AD0IN14 VCCE AD0IN15 AVSS0
VREF1 AVCC1
VSS
VCCI
AD0IN10 AD0IN13 AD0IN11 AD0IN12
AD1IN2 AD1IN3 AD1IN1 AD1IN0
AD0IN6 AD0IN9 AD0IN7 AD0IN8
AD1IN6 AD1IN7 AD1IN5 AD1IN15
P45
/CS1
P46
/A13
P47
/A14
P220
/CTX
P221
/CRX
P225
/A12
XOUT
VSS
P33
/A18
P34
/A19
P35
/A20
TRSYNC
P21
/A24
VSS
P27
/A30
P02
/DB2
P01
/DB1
P00
/DB0
P03
/DB3
P06
/DB6
P05
/DB5
P04
/DB4
P07
/DB7
P10
/DB8
P11
/DB9
P14
/DB12
P13
/DB11
P12
/DB10
AD0IN5 AD0IN3 AD0IN4
AD1IN8 AD1IN10 AD1IN4 AVSS1
P222
VSS
OSC-
VCC
P30
/A15
P31
/A16
P32
/A17
P20
/A23
P37
/A22
P36
/A21
VCCE
P26
/A29
P25
/A28
P24
/A27
AD0IN1 AD0IN0 AD0IN2
AD1IN9 AD1IN11 AD1IN13
P43
/RD
P44
/CS0
P223
OSC-
VSS
VSS
P23
/A26
P22
/A25
VSS
P17
/DB15
P15
/DB13
VREF0
AVCC0
AD1IN12 AD1IN14
P224
/A11
XIN
VCNT
TRCLK
VCCE
P16
/DB14
N.C
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
Package 255FBGA
Note 1: NC pin (W19, Y1) shows non-connect. Be open state.
Note 2: Use caution when using P224/A11 and P225/A12 because they have a debug event function.
Note 3: 255FBGA is currently under development.
Figure 2 Pin Layout Diagram of the 255FBGA
3
2001-5-14 Rev.1.0
Mitsubishi Microcomputers
32170 Group, 32174 Group
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170/32174
Internal bus
interface
DMAC
(10 channels)
M32R CPU core
(max 40MHz)
Multiplier-
accumulator
(32
×
16 + 56)
Multijunction timer
(MJT : 64 channels)
Internal flash memory
( M32170F6 : 768KB )
( M32170F4 : 512KB )
( M32170F3 : 384KB )
( M32174F4 : 512KB )
( M32174F3 : 384KB )
Internal 32-bit bus
Internal 16-bit bus
A-D converter
(10-bit, 16 channels)
×
2
Serial I/O
(6 channels)
Interrupt controller
(31 sources, 8 levels)
Wait controller
Internal RAM
( M32170F6 : 40KB )
( M32170F4 : 32KB )
( M32170F3 : 32KB )
( M32174F4 : 40KB )
( M32174F3 : 40KB )
Full CAN
(1 channel)
Real-time debugger
(RTD)
PLL clock generation
circuit
External bus
interface
Address
Data
Input/output port(JTAG) 157 lines
Figure 3 Block diagram
4
2001-5-14 Rev.1.0
Mitsubishi Microcomputers
32170 Group, 32174 Group
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Table 3 Outline Performance (1/2)
Functional Block
M32R CPU core
Features
M32R family CPU core, internally configured in 32 bits
Built-in multiplier-accumulator (32
×
16 + 56)
Basic bus cycle : 25 ns (Internal CPU clock frequency at 40 MHz, Internal peripheral
clock frequency at 20 MHz)
Logical address space : 4G bytes, linear
General-purpose register : 32-bit register
×
16, Control register: 32-bit register
×
5
accumulator : 56 bits
External data bus
Instruction set
16 bits data bus
16-bit/32-bit instruction formats
83 instructions/ 9 addressing modes
Internal flash memory
M32170F6 : 768K bytes
M32170F4, M32174F4 : 512K bytes
M32170F3, M32174F3 : 384K bytes
Rewrite durability : 100 times
Internal RAM
M32170F6, M32174F4, M32174F3 : 40K bytes
M32170F4, M32170F3 : 32K bytes
DMAC
10 channels (DMA transfers between internal peripheral I/Os, between internal peripheral
I/O and internal RAM, and between internal RAMs)
Channels can be cascaded and can operate in combination with internal peripheral I/O
Multijunction timer
64 channels of multijunction timers.
• 16-bit output-related timers
×
35 channels (single-shot, delayed single-shot, PWM, single-shot PWM)
• 16-bit input/output-related timers
×
10 channels (event count mode, single-shot, PWM, measurement)
• 16-bit input-related timers
×
11 channels (measurement, event count mode, multiply-by-4 count 3 channels)
• 32-bit input-related timers
×
8 channels (measurement)
Flexible timer configuration is possible through interconnection of channels using the event bus.
A-D converter
2 independent 10-bit multifunction A-D converters
• Input 16 channels
×
2
• Scan-based conversion can be switched with 4, 8, and 16
• Capable of interrupt conversion during scan
• 8-bit/10-bit readout function available
Serial I/O
6 channels (The serial I/Os can be set for synchronous serial I/O or UART.
SIO2,3 are UART mode only)
Real-time debugger (RTD)
1-channels dedicated clock-synchronized serial
The entire internal RAM can be read or rewritten from the outside without CPU intervention.
Interrupt controller
Controls interrupts from internal peripheral I/Os
(Priority can be set to one of 8 levels including interrupt disabled)
Wait controller
Controls wait when accessing external extended area
(1 to 4 wait cycles inserted + prolonged by external WAIT signal input)
CAN
JTAG
16-channels message slots
Boundary-Scan function
5