PALCE16V8
PALCE16V8Z
COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25
COM’L:-25
IND:-12/15/25
PALCE16V8 and PALCE16V8Z Families
EE CMOS (Zero-Power) 20-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x
Pin and function compatible with all 20-pin PAL
®
devices
x
Electrically erasable CMOS technology provides reconfigurable logic and full testability
x
High-speed CMOS technology
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The
macrocells provide a universal device architecture. The PALCE16V8 will directly replace the
PAL16R8, with the exception of the PAL16C1.
The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALCE16V8Z allows battery-powered operation for an extended period.
The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
Publication#
16493
Amendment/0
Rev: F
Issue Date:
September 2000
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— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
Direct plug-in replacement for the PAL16R8 series
Outputs programmable as registered or combinatorial in any combination
Peripheral Component Interconnect (PCI) compliant
Programmable output polarity
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on power up
Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
Extensive third-party software and programmer support
Fully tested for 100% programming and functional yields and high reliability
5-ns version utilizes a split leadframe for improved performance
BLOCK DIAGRAM
I1 – I8
CLK/I0
8
Programmable AND Array
32 x 64
MC
0
MC
1
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MC
2
MC
3
MC
4
MC
5
I/O
2
I/O
3
I/O
4
I/O
5
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
R
MC
6
I/O
6
MACRO
MACRO
MC
7
OE
/I
9
I/O
0
I/O
1
I/O
7
16493E-1
FUNCTIONAL DESCRIPTION
The PALCE16V8 is a universal PAL device. The PALCE16V8Z is the zero-power version of the
PALCE16V8. It has all the architectural features of the PALCE16V8. In addition, the PALCE16V8Z
has zero standby power and an unused product term disable feature for reduced power
consumption. It has eight independently configurable macrocells (MC
0
-
MC
7
). Each macrocell can
be configured as registered output, combinatorial output, combinatorial I/O or dedicated input.
The programming matrix implements a programmable AND logic array, which drives a fixed OR
logic array. Buffers for device inputs have complementary outputs to provide user-
programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK)
and output enable (OE), respectively, for all flip-flops.
Unused input pins should be tied directly to V
CC
or GND. Product terms with all bits
unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALCE16V8 are automatically configured from the user’s
design specification. The design specification is processed by development software to verify
the design and create a programming file (JEDEC). This file, once downloaded to a programmer,
configures the device according to the user’s desired function.
The user is given two design options with the PALCE16V8. First, it can be programmed as a
standard PAL device from the PAL16R8 series. The PAL programmer manufacturer will supply
device codes for the standard PAL device architectures to be used with the PALCE16V8.
The programmer will program the PALCE16V8 in the corresponding architecture. This allows
the user to use existing standard PAL device JEDEC files without making any changes to them.
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PALCE16V8 and PALCE16V8Z Families
Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the
PALCE16V8 device code. This option allows full utilization of the macrocell.
To
Adjacent
Macrocell
11
0X
10
OE
V
CC
11
10
00
01
SL0
X
SG1
R
11
0X
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I/O
X
D
Q
Q
SL1
X
CLK
10
11
0X
SL0
X
*SG1
*In macrocells MC
0
and MC
7
, SG1 is replaced by SG0 on the feedback multiplexer.
From
Adjacent
Pin
16493E-2
Figure 1. PALCE16V8 Macrocell
CONFIGURATION OPTIONS
Each macrocell can be configured as one of the following: registered output, combinatorial
output, combinatorial I/O, or dedicated input. In the registered output configuration, the output
buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled
by a product term or always enabled. In the dedicated input configuration, it is always disabled.
With the exception of MC
0
and MC
7
, a macrocell configured as a dedicated input derives the
input signal from an adjacent I/O. MC
0
derives its input from pin 11 (OE) and MC
7
from pin 1
(CLK).
The macrocell configurations are controlled by the configuration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL0
0
through SL0
7
and SL1
0
through SL1
7
). SG0
determines whether registers will be allowed. SG1 determines whether the PALCE16V8 will
emulate a PAL16R8 family or a PAL10H8 family device. Within each macrocell, SL0
x
, in
conjunction with SG1, selects the configuration of the macrocell, and SL1
x
sets the output as
either active low or active high for the individual macrocell.
The configuration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0
x
are the control signals for all four multiplexers. In
MC
0
and MC
7
, SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being
the adjacent pin for MC
7
and OE the adjacent pin for MC
0
.
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PALCE16V8 and PALCE16V8Z Families
3
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0
x
= 0. There is only one registered
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1
x.
The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback
path is from Q on the register. The output buffer is enabled by OE.
Combinatorial Configurations
The PALCE16V8 has three combinatorial output configurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0
x
= 0. All eight product terms are available
to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK
and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin
1 will use the feedback path of MC
7
, and pin 11 will use the feedback path of MC
0
.
Combinatorial I/O in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0
x
= 1. Only seven product terms are
available to the OR gate. The eighth product term is used to enable the output buffer. The signal
at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to
be used as an input.
Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as
inputs. Pin 1 will use the feedback path of MC
7
, and pin 11 will use the feedback path of MC
0
.
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0
x
= 1. Only seven product terms are available
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Dedicated Input Configuration
The control bit settings are SG0 = 1, SG1 = 0 and SL0
x
= 1. The output buffer is disabled. Except
for MC
0
and MC
7
, the feedback signal is an adjacent I/O. For MC
0
and MC
7
, the feedback signals
are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.
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SG0
SG1
SL0X
Cell
Configuration
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Table 1. Macrocell Configuration
Devices
Emulated
SG0
SG1
SL0X
PAL16R8, 16R6,
16R4
1
0
0
PAL16R6, 16R4
1
0
1
1
1
1
R
Cell
Configuration
Devices
Emulated
Device Uses Registers
0
1
0
Registered Output
Device Uses No Registers
Combinatorial
Output
PAL10H8, 12H6,
14H4, 16H2, 10L8,
12L6, 14L4, 16L2
PAL12H6, 14H4,
16H2, 12L6, 14L4,
16L2
PAL16L8
0
1
1
Combinatorial
I/O
Input
Combinatorial
I/O
4
PALCE16V8 and PALCE16V8Z Families
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output signal
needs or to reduce product terms. Programmable polarity allows Boolean expressions to be
written in their most compact form (true or inverted), and the output can still be of the desired
polarity. It can also save “DeMorganizing” efforts.
Selection is through a programmable bit SL1
x
which controls an exclusive-OR gate at the output
of the AND/OR logic. The output is active high if SL1
x
is 1 and active low if SL1
x
is 0.
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PALCE16V8 and PALCE16V8Z Families
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嵌入式系统
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