COM'L: H-5/7/10/15/25, Q-10/15/25
IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x
Pin and function compatible with all PAL
®
20V8 devices
x
Electrically erasable CMOS technology provides reconfigurable logic and full testability
x
High-speed CMOS technology
x
x
x
x
x
x
x
x
x
x
x
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
Direct plug-in replacement for a wide range of 24-pin PAL devices
Programmable enable/disable control
Outputs individually programmable as registered or combinatorial
Peripheral Component Interconnect (PCI) compliant
Preloadable output registers for testability
Automatic register reset on power-up
Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages
Extensive third-party software and programmer support
Fully tested for 100% programming and functional yields and high reliability
Programmable output polarity
5-ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. Its macrocells provide a universal device architecture. The
PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.
Device logic is automatically configured according to the user’s design specification. A design is
implemented using any of a number of popular design software packages, allowing automatic
creation of a programming file based on Boolean or state equations. Design software also verifies
the design and can provide test vectors for the finished device. Programming can be
accomplished on standard PAL device programmers.
The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
Publication#
16491
Amendment/0
Rev:
E
Issue Date:
November 1998
The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
BLOCK DIAGRAM
I1 – I10
CLK/I
0
10
Programmable AND Array
40 x 64
Input
Mux.
MACRO
MC
0
MACRO
MC
1
MACRO
MC
2
MACRO
MC
3
MACRO
MC
4
MACRO
MC
5
MACRO
MC
6
MACRO
MC
7
Input
Mux.
OE
/I
11
I
12
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I
13
16491E
FUNCTIONAL DESCRIPTION
The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells
(MC
0
-MC
7
). Each macrocell can be configured as a registered output, combinatorial output,
combinatorial I/O, or dedicated input. The programming matrix implements a programmable
AND logic array, which drives a fixed OR logic array. Buffers for device inputs have
complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve
either as array inputs or as clock (CLK) and output enable (OE) for all flip-flops.
Unused input pins should be tied directly to V
CC
or GND. Product terms with all bits
unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALCE20V8 are automatically configured from the user’s
design specification, which can be in a number of formats. The design specification is processed
2
PALCE20V8 Family
by development software to verify the design and create a programming file. This file, once
downloaded to a programmer, configures the device according to the user’s desired function.
The user is given two design options with the PALCE20V8. First, it can be programmed as an
emulated PAL device. This includes the PAL20R8 series and most 24-pin combinatorial PAL
devices. The PAL device programmer manufacturer will supply device codes for the standard
PAL architectures to be used with the PALCE20V8. The programmer will program the PALCE20V8
to the corresponding PAL device architecture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to them. Alternatively, the device can be
programmed directly as a PALCE20V8. Here the user must use the PALCE20V8 device code. This
option provides full utilization of the macrocells, allowing non-standard architectures to be built.
To
Adjacent
Macrocell
11
0X
10
OE
V
CC
11
10
00
01
SL0
X
SG1
11
0X
D
SL1
X
CLK
Q
Q
10
11
0X
*SG1
*In macrocells MC
0
and MC
7
, SG1 is replaced by SG0 on the feedback multiplexer.
16491E
I/O
X
10
SL0
X
From
Adjacent
Pin
Figure 1. PALCE20V8 Macrocell
PALCE20V8 Family
3
CONFIGURATION OPTIONS
Each macrocell can be configured as one of the following: registered output, combinatorial
output, combinatorial I/O or dedicated input. In the registered output configuration, the output
buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled
by a product term or always enabled. In the dedicated input configuration, the buffer is always
disabled. A macrocell configured as a dedicated input derives the input signal from an adjacent
I/O.
The macrocell configurations are controlled by the configuration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL0
0
through SL0
7
and SL1
0
through SL1
7
). SG0
determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will
emulate a PAL20R8 family or a combinatorial device. Within each macrocell, SL0
x
, in conjunction
with SG1, selects the configuration of the macrocell and SL1
x
sets the output as either active low
or active high.
The configuration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0
x
are the control signals for all four multiplexers. In MC
0
and MC
7
, SG0 replaces SG1 on the feedback multiplexer.
These configurations are summarized in Table 1 and illustrated in Figure 2.
If the PALCE20V8 is configured as a combinatorial device, the CLK and OE pins may be available
as inputs to the array. If the device is configured with registers, the CLK and OE pins cannot be
used as data inputs.
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0
x
= 0. There is only one registered
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1
x
. SL1
x
is an input to the exclusive-OR gate which is the D input to the flip-
flop. SL1
x
is programmed as 1 for inverted output or 0 for non-inverted output. The flip-flop is
loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The
output buffer is enabled by OE.
Combinatorial Configurations
The PALCE20V8 has three combinatorial output configurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control settings are SG0 = 1, SG1 = 0, and SL0
x
= 0. All eight product terms are available to
the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode.
Note:
1. The pin number without parentheses refers to the SKINNY DIP package. The pin number in parentheses refers to the PLCC
package.
4
PALCE20V8 Family
Dedicated Input in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0
x
= 1. The output buffer is disabled. The
feedback signal is an adjacent I/O pin.
Combinatorial I/O in a Non-Registered Device
The control settings are SG0 = 1, SG1 = 1, and SL0
x
= 1. Only seven product terms are available
to the OR gate. The eighth product term is used to enable the output buffer. The signal at the
I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used
as an input.
Combinatorial I/O in a Registered Device
The control bit settings are SG0=0,SG1=1 and SL0
x
=1. Only seven product terms are available
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Table 1. Macrocell Configuration
SG0
SG1
SL0X
Cell
Configuration
Devices
Emulated
SG0
SG1
SL0X
Cell
Configuration
Devices
Emulated
Device Uses Registers
0
0
1
1
0
1
Registered Output
Combinatorial
I/O
PAL20R8, 20R6,
20R4
PAL20R6, 20R4
1
1
1
0
0
1
Device Uses No Registers
0
1
1
Combinatorial
Output
Input
Combinatorial
I/O
PAL20L2, 18L4,
16L6, 14L8
PAL20L2, 18L4, 16L6
PAL20L8
PALCE20V8 Family
5
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