IDT5V928
8 OUTPUT CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
8 OUTPUT
CLOCK GENERATOR
IDT5V928
FEATURES:
•
•
•
•
•
•
•
•
3V to 3.6V operating voltage
50MHz to 160MHz output frequency range
Input from fundamental crystal oscillator or external source
Internal PLL feedback (loading feedback output relative to
other outputs, adjusts propagation delay between REF inputs
and outputs)
Select inputs (S
[1:0]
) for FB divide selection (multiply ratio of 2,
3, 4, 4.25, 5, 6, 6.25, and 8)
Low jitter
PLL bypass for testing and power-down control (S1 = H, S0 = H,
powers part down <500µA)
µ
Available in TSSOP package
The IDT5V928 is a low-cost, low skew, low jitter, and high-performance
clock synthesizer. It has been specially designed to interface with Gigabit
Ethernet (125MHz), Fibre CHannel (106.25MHz), and OC-3 (155.52MHz)
applications. It can be programmed to provide output frequencies ranging
from 50MHz to 160MHz, with input frequencies ranging from 6.25MHz to
80MHz.
The IDT5V928 includes an internal RC filter that provides excellent jitter
characteristics and eliminates the need for external components. When
using the optional crystal input, the chip accepts a 10 - 40MHz fundamental
mode crystal with a maximum equivalent series resistance of 50Ω.
DESCRIPTION:
APPLICATIONS:
•
•
•
•
•
•
Gigabit ethernet
Router
Network switches
SAN
Instrumentation
Fibre channel
FUNCTIONAL BLOCK DIAGRAM
OE
VCO DIVIDE
1/N
Q
0
REF
PH AS E
DETEC TO R
CH ARGE
PU M P
LO OP
FILTER
VC O
Q
1
Q
2
0
Q
3
1
Q
4
Q
5
X2
CRY STAL
OSCILLATO R
X1
Q
6
SELECT MO D E
Q
7
S1
S0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2003
Integrated Device Technology, Inc.
FEBRUARY 2003
DSC
5854/5
IDT5V928
8 OUTPUT CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
REF
X
1
X
2
V
DD
V
DDQ
Q
0
Q
1
GND
GND
Q
2
Q
3
V
DDQ
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
S
0
S
1
OE
GND
V
DDQ
Q
7
Q
6
GND
GND
Q
5
Q
4
V
DDQ
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DD
/V
DDQ
V
I
I
O
T
STG
T
J
Description
Supply Voltage to Ground
Input Voltage
Output Current
Storage Temperature
Junction Temperature
Max.
– 0.5 to +4.6
– 0.5 to +4.6
±50
– 65 to +150
150
Unit
V
V
mA
°C
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Name Type
S[
1:0
]
I
I
OE
Description
Three level divider/mode select pins. Float to MID.
Output enable bar.
OE
has a pull-down. Output Q
[1:7]
tristated
when HIGH. Output Q
0
remains running when in PLL mode
and tri-states when in TEST mode.
Crystal oscillator input. Connect to GND if oscillator not
required.
Crystal oscillator output. Leave unconnected for clock input.
Input clock. Connect to X
2
if crystal oscillator is used.
Output at N*REF frequency
Output at N*REF internally connected for PLL feedback
Power supply for the device outputs. Connect to V
DD
on PCB.
Power supply for the device core and inputs. Connect to V
DD
on PCB.
GND
PWR
Ground supply
TSSOP
TOP VIEW
X
1
I
I
I
O
O
PWR
PWR
CRYSTAL SPECIFICATION
The crystal oscillators should be fundamental mode quartz crystals:
overtone crystals are not suitable. Crystal frequency should be specified
for parallel resonance with 50Ω maximum equivalent series resonance.
Crystal tuning capacitors should be connected from X
2
/REF to GND and from
X
1
to GND.
X
2
REF
Q
[1:7]
Q
0
V
DDQ
V
DD
DIVIDE SELECTION TABLE
(1)
S1
L
L
L
M
M
M
H
H
H
S0
L
M
H
L
M
H
L
M
H
Divide-by-N Value
2
3
4
4.25
5
6
6.25
8
TEST
Mode
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
TEST
(2)
NOTES:
1. H = HIGH
M = MEDIUM
L = LOW
2. Test mode for low frequency testing. In this mode, REF clock bypasses the VCO (VCO powered down) and the crystal oscillator is powered down.
2
IDT5V928
8 OUTPUT CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
COMMON OUTPUT FREQUENCY EXAMPLES (MHz)
Output
Input
FB Divide Selection S[
1:0
]
Output
Input
FB Divide Selection S[
1:0
]
50
25
LL
106.25
17
HL
60
10
MH
106.25
25
ML
64
16
LH
120
15
HM
72
12
MH
125
20
HL
75
25
LM
125
25
MM
80
10
HM
125
62.5
LL
90
15
MH
150
25
MH
100
20
MM
155.52
19.44
HM
OPERATING CONDITIONS
Symbol
V
DD
/V
DDQ
T
A
C
L
C
IN
Parameter
Power Supply Voltage
Operating Temperature
Output Load Capacitance
Input Capacitance, OE, F = 1MHz, V
IN
= 0V, T
A
= 25°C
Min.
3
- 40
—
—
Typ.
3.3
25
—
5
Max.
3.6
+85
15
7
Unit
V
°C
pF
pF
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
DD
/V
DDQ
= 3.3V ±0.3V
Symbol
V
IL
V
IH
V
IHH
V
IMM
V
ILL
I
IN
I
3
I
IH
V
OL
V
OH
Parameter
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Input MID Voltage
Input LOW Voltage
Input Leakage Current (REF input only)
3-Level Input DC Current, S
[1:0]
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Test Conditions
Min.
—
2
V
DD
- 0.6
V
DD
/2 - 0.3
—
-5
—
- 50
- 200
—
—
2.4
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
Max
0.8
—
—
V
DD
/2 + 0.3
0.6
+5
+200
+50
—
100
0.4
—
Unit
V
V
V
V
V
µA
µA
µA
V
V
3-level input only
3-level input only
3-level input only
V
IN
= V
DD
or GND,V
DD
= Max.
V
IN
= V
DD
HIGH Level
V
IN
= V
DD
/2
MID Level
V
IN
= GND
LOW Level
V
IN
= V
DD
I
OL
= 12mA
I
OH
= -12mA
3
IDT5V928
8 OUTPUT CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
I
DD_PD
Parameter
Power Down Current
Test Conditions
(1)
V
DD
= Max.
S
[1:0]
= HH
OE
= L
;
REF = L; X
1
= L
All outputs unloaded
∆I
DD
I
DD
Supply Current per Input
Dynamic Supply Current
V
DD
= Max., V
IN
= 3V
V
DD
= 3.6V
S
[1:0]
= LL
OE
= L
F
OUT
= 150MHz
All outputs unloaded
NOTE:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
Min.
—
Typ.
—
Max
500
Unit
µA
—
—
—
—
30
130
µA
mA
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
R,
t
F
d
T
t
PD
t
SK
t
J
f
OUT
Parameter
Rise Time, Fall Time
Output/Duty Cycle
REF to Q
0
(1)
Output to Output Skew (Q
0
to Q
1:7
)
Cycle - Cycle Jitter
Output Frequency
0.8V to 2V
V
T
= V
DDQ
/2
f
OUT
≥
100MHz, all N
V
T
= V
DDQ
/2
Equal loads
f
OUT
≥
100MHz
50 < f
OUT
< 160MHz, N
≤
4
50 < f
OUT
< 160MHz, N
≥
4.25
Test Conditions
Min.
—
45
-200
-200
-350
—
-100
50
Typ.
0.7
50
—
—
—
—
—
—
Max.
1.5
55
200
200
350
200
100
160
ps
ps
MHz
ps
Unit
ns
%
NOTE:
1. When using a clock input.
INPUT TIMING REQUIREMENTS
Symbol
t
R,
t
F
t
PWC
D
H
f
OSC
f
IN
Description
(1)
Maximum input rise and fall time, 0.8V to 2V
(2)
Input clock pulse, HIGH or LOW
(2)
Input duty cycle
(2)
XTAL oscillator frequency
Input frequency
(2)
Min.
—
2
10
—
50/N
Max.
10
—
90
40
160/N
Unit
ns/V
ns
%
MHz
MHz
NOTES:
1. Where pulse width implied by D
H
is less than the t
PWC
limit, t
PWC
limit applies,
2. When using a clock input.
4
IDT5V928
8 OUTPUT CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
AC TEST LOADS AND WAVEFORMS
V
DD
150
Ω
OUTPUT
15pF
150
Ω
AC Test Load
3V
2V
V
TH
= V
D D
/2
0.8
0V
1ns
1ns
Input Test Waveform
V
DDQ
2V
V
TH
= V
D DQ
/2
0.8
0V
t
R
t
F
Output Waveform
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
