HD74AC194
4-bit Bidirectional Unviersal Shift Register
REJ03D0259–0200Z
(Previous ADE-205-379 (Z))
Rev.2.00
Jul.16.2004
Description
This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a
shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control
inputs, and a direct overriding clear line. The register has four destinct modes of operation: parallel (broadside) load,
shift right (in the direction Q
0
toward Q
3
); shift left; inhibit clock (do nothing).
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S
0
and S
1
, high. The data are loaded into their respective flip-flops and appear at the output after the positive transition of
the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising
edge of the clock pulse when S
0
is high and S
1
is low. Serial date for this mode is entered at the shift right data input.
When S
0
is low and S
1
is high, data shifts left synchronously and new data is entered at the shifts left serial input.
Clocking of the flip-flops is inhibited when both mode control inputs are low. The mode control inputs should be
changed only when the clock input is high.
Features
•
Asynchronous Master Reset
•
Hole (Do Nothing) Mode
•
Outputs Source/Sink 24 mA
•
Ordering Information
Part Name
HD74AC194FPEL
HD74AC194RPEL
Package Type
SOP-16 pin (JEITA)
Package Code Package Abbreviation Taping Abbreviation (Quantity)
FP-16DAV
FP
RP
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
SOP-16 pin (JEDEC) FP-16DNV
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Rev.2.00, Jul.16.2004, page 1 of 7
HD74AC194
Pin Names
S
0
, S
1
P
0
to P
3
D
SR
D
SL
CP
MR
Q
0
to Q
3
Mode Control Inputs
Parallel Data Inputs
Serial Data Input (Shift Right)
Serial Data Input (Shift Left)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Outputs
Logic Diagram
D
SL
P
3
P
2
P
1
P
0
D
SR
S
0
S
1
D
C
C Q
CL CL
D
C
C Q
CL CL
D
C
C Q
CL CL
D
C
C Q
CL CL
CP
MR
Q
3
Q
2
Q
1
Q
0
Mode Select Table
Operating Mode
Reset
Hold
Shift Left
Shift Right
L
H
H
H
H
H
MR
X
L
H
H
L
L
S
1
X
L
L
L
H
H
Inputs
S
0
D
SR
X
X
X
X
L
H
X
X
L
H
X
X
Output
D
SL
X
X
X
X
X
X
P
n
L
q
0
q
1
q
1
L
H
Q
0
L
q
1
q
2
q
2
q
0
q
0
Q
1
L
q
2
q
3
q
3
q
1
q
1
Q
2
L
q
3
L
H
q
2
q
2
Q
3
Parallel Load
H
H
H
X
X
p
n
p
0
p
1
p
2
p
3
H
: HIGH Voltage Level
L
: LOW Voltage Level
p
n
(q
n
) : Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH
clock transition
X
: Immaterial
Rev.2.00, Jul.16.2004, page 3 of 7
HD74AC194
Timing Diagram
CP
Mode
Control
Inputs
S
1
MR
Parallel
Data
Inputs
D
SH
D
SL
P
0
Parallel
Data
Inputs
P
2
P
3
Q
0
Outputs
Q
1
Q
2
Q
3
Shift Right
Clear
Load
Shift Left
Inhibit
Clear
H
L
P
1
H
L
S
0
Absolute Maximum Ratings
Item
Supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or ground current per output pin
Storage temperature
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
, I
GND
Tstg
Ratings
–0.5 to 7
–20
20
–0.5 to Vcc+0.5
–50
50
–0.5 to Vcc+0.5
±50
±50
–65 to +150
Unit
V
mA
mA
V
mA
mA
V
mA
mA
°C
V
I
= –0.5V
V
I
= Vcc+0.5V
V
O
= –0.5V
V
O
= Vcc+0.5V
Condition
Recommended Operating Conditions
Item
Supply voltage
Input and output voltage
Operating temperature
Input rise and fall time
(except Schmitt inputs)
V
IN
30% to 70% V
CC
Symbol
V
CC
V
I
, V
O
Ta
tr, tf
2 to 6
0 to V
CC
–40 to +85
8
Ratings
V
V
°C
ns/V
V
CC
= 3.0V
V
CC
= 4.5 V
V
CC
= 5.5 V
Unit
Condition
Rev.2.00, Jul.16.2004, page 4 of 7
HD74AC194
DC Characteristics
Item
Sym-
bol
V
IH
Vcc
(V)
3.0
4.5
5.5
V
IL
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
V
OL
5.5
3.0
4.5
5.5
3.0
4.5
Input leakage
current
Dynamic output
current*
Quiescent supply
current
I
IN
I
OLD
I
OHD
I
CC
5.5
5.5
5.5
5.5
5.5
min.
2.1
3.15
3.85
—
—
—
2.9
4.4
5.4
2.58
3.94
4.94
—
—
—
—
—
—
—
—
—
—
Ta = 25°C
°
typ.
1.5
2.25
2.75
1.50
2.25
2.75
2.99
4.49
5.49
—
—
—
0.002
0.001
0.001
—
—
—
—
—
—
—
max.
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.32
0.32
0.32
±0.1
—
—
8.0
Ta = –40 to
+85°C
°
min.
2.1
3.15
3.85
—
—
—
2.9
4.4
5.4
2.48
3.80
4.80
—
—
—
—
—
—
—
86
–75
—
max.
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.37
0.37
0.37
±1.0
—
—
80
µA
mA
mA
µA
V
V
OUT
= 0.1 V or V
CC
–0.1 V
Unit
Condition
Input Voltage
V
V
OUT
= 0.1 V or V
CC
–0.1 V
Output voltage
V
OH
V
IN
= V
IL
or V
IH
I
OUT
= –50
µA
V
IN
= V
IL
or V
IH
I
OH
= –12 mA
I
OH
= –24 mA
I
OH
= –24 mA
V
IN
= V
IL
or V
IH
I
OUT
= 50
µA
V
IN
= V
IL
or V
IH
I
OL
= 12 mA
I
OL
= 24 mA
I
OL
= 24 mA
V
IN
= V
CC
or GND
V
OLD
= 1.1 V
V
OHD
= 3.85 V
V
IN
= V
CC
or ground
*Maximum
test duration 2.0 ms, one output loaded at a time.
AC Characteristics
Ta = +25°C
C
L
= 50 pF
Min
Typ
Max
75
100
1.0
1.0
1.0
1.0
1.0
1.0
—
—
—
—
—
—
—
—
13.0
10.0
13.0
10.0
10.5
8.0
Ta = –40°C to +85°C
C
L
= 50 pF
Min
Max
65
85
1.0
1.0
1.0
1.0
1.0
1.0
15.0
11.5
15.0
11.5
12.5
9.0
MHz
ns
ns
ns
Item
Maximum clock
frequency
Propagation delay
CP to Q
n
Propagation delay
CP to Q
n
Propagation delay
MR
to Q
n
Note:
Symbol
f
max
t
PLH
t
PHL
t
PHL
V
CC
(V)*
1
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Unit
1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 7
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