5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
5832
BiMOS II 32-BIT SERIAL-INPUT,
LATCHED DRIVERS
Intended originally to drive thermal printheads, the UCN5832A
and UCN5832EP have been optimized for low output-saturation
voltage, high-speed operation, and pin configurations most convenient
for the tight space requirements of high-resolution printheads. These
integrated circuits can also be used to drive multiplexed LED displays
or incandescent lamps at up to 150 mA peak current. The combination
of bipolar and MOS technologies gives BiMOS II arrays an interface
flexibility beyond the reach of standard buffers and power driver
circuits.
The devices each have 32 bipolar NPN open-collector saturated
drivers, a CMOS data latch for each of the drivers, two 16-bit CMOS
shift registers, and CMOS control circuitry. The high-speed CMOS
shift registers and latches allow operation with most microprocessor
based systems. Use of these drivers with TTL may require input
pull-up resistors to ensure an input logic high. MOS serial data
outputs permit cascading for interface applications requiring additional
drive lines.
The UCN5832A is supplied in a 40-pin dual in-line plastic package
with 0.600" (15.24 mm) row spacing. Under normal operating condi-
tions, this device will allow all outputs to sustain 100 mA continuously
without derating. The UCN5832EP is supplied in a 44-lead plastic
leaded chip carrier for minimum area, surface-mount applications.
Both devices are also available for operation from -40°C to +85°C.
To order, change the prefix from ‘UCN’ to ‘UCQ’.
Similar 32-bit serial-input latched source drivers are available as
the UCN5818AF/EPF. Other high-voltage, high-current 8-bit devices
are available as the UCN5821A, UCN5841A/LW, and UCN5842A.
Data Sheet
26185.10B
UCN5832A
LOGIC
SUPPLY
SERIAL
DATA IN
GROUND
STROBE
OUT 1
OUT
OUT
OUT
2
3
1
2
3
4
5
6
7
8
REGISTER
REGISTER
LATCHES
V
DD
40
CLOCK
39
38
37
36
35
34
33
32
SERIAL
DATA OUT
OUTPUT
ENABLE
OUT 32
OUT
OUT
31
30
OUT 29
OUT
28
4
5
6
OUT
10
11
12
12
LATCHES
OUT
9
OUT 27
26
31
OUT
OUT 7
OUT
8
30
OUT 25
29
28
27
26
25
24
OUT 24
OUT 23
OUT 22
OUT 21
OUT 20
OUT 19
OUT 9
OUT 10
14
OUT 11
15
OUT 12
16
OUT 13
17
OUT 14
18
OUT 15
19
OUT 16
20
23
OUT 18
22
OUT 17
21
INTERNAL
CONNECTION
Dwg. No. A-12,377A
ABSOLUTE MAXIMUM RATINGS
at +25°C Free-Air Temperature
Output Voltage, V
OUT
......................
40 V
Logic Supply Voltage, V
DD
................
15 V
Input Voltage Range,
V
IN
...................
-0.3 V to V
DD
+ 0.3 V
Continuous Output Current,
l
OUT
..................................
150 mA
Package Power Dissipation,
P
D
................................
See Graph
Operating Temperature Range,
T
A
...........................
-20
°
C to +85
°
C
Storage Temperature Range,
T
S
..........................
-55
°
C to +150
°
C
Caution: CMOS devices have input-static
protection but are susceptible to damage when
exposed to extremely high static electrical charges.
FEATURES
s
s
s
s
s
To 3.3 MHz Data Input Rate
Low-Power CMOS Logic and Latches
40 V Current Sink Outputs
Low Saturation Voltage
Automotive Capable
Always order by complete part number:
Part Number
UCN5832A
UCN5832EP
Package
40-Pin DIP
44-Lead PLCC
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
3.0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
FUNCTIONAL BLOCK DIAGRAM
2.5
SUFFIX 'A', R
θJA
= 36°C/W
V
DD
CLOCK
32-BIT SHIFT REGISTER
2.0
SERIAL
DATA IN
LATCHES
SERIAL DATA
OUT
1.5
SUFFIX 'EP', R
θJA
= 46°C/W
STROBE
1.0
OUTPUT
ENABLE
MOS
BIPOLAR
0.5
OUT
1
OUT
2
OUT
3
GROUND OUT
30
OUT
31
OUT
32
0
25
50
75
100
125
AMBIENT TEMPERATURE IN
°C
150
Dwg. GP-025A
UCN5832EP
SERIAL
DATA OUT
32
GROUND
STROBE
OUTPUT
ENABLE
LOGIC
SUPPLY
SERIAL
DATA IN
CLOCK
OUT
32
41
OUT
1
NC
44
43
V
DD
1
42
40
5
6
4
3
2
NC
OUT
2
7
8
9
10
39
OUT
31
38
37
SHIFT REGISTER
SHIFT REGISTER
36
LATCHES
LATCHES
11
12
13
14
15
16
35
34
33
32
31
30
29
OUT
21
OUT
12
17
OUT
13
19
20
21
OUT
16
22
IC
23
OUT
17
24
25
26
OUT
20
27
NC
18
NC
28
Dwg. No. A-14,360
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1984, 1998, Allegro MicroSystems, Inc.
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C, V
DD
= 5 V (unless otherwise noted).
Characteristic
Output Leakage Current
Collector-Emitter
Saturation Voltage
Symbol
I
CEX
V
CE(SAT)
Test Conditions
V
OUT
= 40 V, T
A
= 70°C
l
OUT
= 50 mA
l
OUT
= 100 mA, “A” package
l
OUT
= 100 mA, “EP” package
Input Voltage
V
IN(1)
V
IN(0)
Input Current
l
IN(1)
l
IN(0)
Input lmpedance
Serial Data Output Resistance
Supply Current
Z
IN
R
OUT
l
DD
One output ON, l
OUT
= 100 mA
All outputs OFF
Output Rise Time
Output Fall Time
t
r
t
f
l
OUT
= 100 mA, 10% to 90%
l
OUT
= 100 mA, 90% to 10%
V
IN
= 3.5 V
V
IN
= 0.8 V
V
IN
= 3.5 V
Min.
—
—
150
—
3.5
-0.3
—
—
3.5
—
—
—
—
—
Limits
Max.
10
275
550
550
5.3
+0.8
1.0
-1.0
—
20
5.0
50
1.0
1.0
Units
µA
mV
mV
mV
V
V
µA
µA
MΩ
kΩ
mA
µA
µs
µs
NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin.
TYPICAL INPUT CIRCUIT
V
DD
TYPICAL OUTPUT DRIVER
V
DD
IN
675Ω
OUT
Dwg. No. A-12,379A
Dwg. No. A-12,380A
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
CLOCK
DATA IN
E
STROBE
OUTPUT
ENABLE
G
OUT
N
Dwg. No. A-12,276A
A
B
D
F
C
Serial Data present at the input is trans-
ferred to the shift register on the logic “0” to
logic “1” transition of the CLOCK input pulse.
On succeeding CLOCK pulses, the registers
shift data information towards the SERIAL
DATA OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge of
the CLOCK input waveform.
Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel conver-
sion). The latches will continue to accept
new data as long as the STROBE is held
high. Applications where the latches are
bypassed (STROBE tied high) will require
that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low,
all of the output buffers are disabled (OFF)
without affecting the information stored in the
latches or shift register. With the OUTPUT
ENABLE input high, the outputs are con-
trolled by the state of the latches.
TIMING CONDITIONS
(V
DD
= 5.0 V, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ..........................................................................
75 ns
B.
Minimum Data Active Time After Clock Pulse
(Data Hold Time) .............................................................................
75 ns
C.
Minimum Data Pulse Width ................................................................
150 ns
D.
Minimum Clock Pulse Width ...............................................................
150 ns
E.
Minimum Time Between Clock Activation and Strobe .......................
300 ns
F.
Minimum Strobe Pulse Width .............................................................
100 ns
G.
Typical Time Between Strobe Activation and
Output Transition ...........................................................................
500 ns
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I
1
I
2
I
3
... I
N-1
I
N
H
L
X
H
L
R
1
R
2
...
R
1
R
2
...
X
X
...
R
N-2
R
N-1
R
N-2
R
N-1
R
N-1
R
N
X
X
P
N-1
P
N
Serial
Data Strobe
Output Input
R
N-1
R
N-1
R
N
X
P
N
L
H
R
1
R
2
R
3
...
P
1
P
2
P
3
...
X
L = Low Logic Level
H = High Logic Level
X = Irrelevant
Latch Contents
I
1
I
2
I
3
...
I
N-1
I
N
Output
Enable
Input
Output Contents
I
1
I
2
I
3
... I
N-1
I
N
R
1
R
2
R
3
...
X
P
1
P
2
P
3
...
R
N-1
R
N
P
N-1
P
N
X
X
H
L
P
1
P
2
P
3
... P
N-1
P
N
H H H ... H
H
X
X
...
P = Present State
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
UCN5832A
Dimensions in Inches
(controlling dimensions)
0.015
0.008
21
40
0.700
MAX
0.580
0.485
0.600
BSC
1
2
0.070
0.030
3
4
2.095
1.980
20
0.100
BSC
0.005
MIN
0.250
MAX
0.015
MIN
0.200
0.115
0.022
0.014
Dwg. MA-003-40 in
Dimensions in Millimeters
(for reference only)
0.381
0.204
21
40
17.78
14.73
12.32
MAX
15.24
BSC
1
2
1.77
0.77
3
4
53.2
50.3
2.54
BSC
20
0.13
MIN
6.35
MAX
0.39
MIN
5.08
2.93
0.558
0.356
Dwg. MA-003-40 mm
NOTES: 1. Lead thickness is measured at seating plane or below.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
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