6273
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
CLEAR
IN
1
IN
2
OUT
1
OUT
2
OUT
3
OUT
4
IN
3
IN
4
GROUND
1
2
3
4
V
DD
20
19
18
17
LOGIC
SUPPLY
IN
8
IN
7
OUT
8
OUT
7
OUT
6
OUT
5
IN
6
IN
5
STROBE
8-BIT LATCHED
DMOS POWER DRIVER
The A6273KA and A6273KLW combine eight (positive-edge-
triggered D-type) data latches and DMOS outputs for systems requiring
relatively high load power. Driver applications include relays, sole-
noids, and other medium-current or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with microproces-
sor-based systems. Use with TTL may require appropriate pull-up
resistors to ensure an input logic high.
The DMOS output inverts the DATA input. All of the output
drivers are disabled (the DMOS sink drivers turned OFF) with the
CLEAR input low. The A6273KA/KLW DMOS open-drain outputs are
capable of sinking up to 750 mA. Similar devices with reduced r
DS(on)
will be available as the A6A273.
The A6273KA is furnished in a 20-pin dual in-line plastic package.
The A6273KLW is furnished in a 20-lead wide-body, small-outline
plastic package (SOIC) with gull-wing leads for surface-mount applica-
tions. Copper lead frames, reduced supply current requirements, and
low on-state resistance allow both devices to sink 150 mA from all
outputs continuously, to ambient temperatures over 85°C.
Data Sheet
26180.120
LATCHES
LATCHES
5
6
7
8
9
10
16
15
14
13
12
11
Dwg. PP-015-2
Note that the A6273KA (DIP) and the A6273KLW
(SOIC) are electrically identical and share a com-
mon terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25
°
C
Output Voltage, V
O
.............................
50 V
Output Drain Current,
Continuous, I
O
.......................
250 mA*
Peak, I
OM
..............................
750 mA*†
Peak, I
OM
.....................................
2.0 A†
Single-Pulse Avalanche Energy,
E
AS
..............................................
75 mJ
Logic Supply Voltage, V
DD
................
7.0 V
Input Voltage Range,
V
I
.................................
-0.3 V to +7.0 V
Package Power Dissipation,
P
D
........................................
See Graph
Operating Temperature Range,
T
A
..............................
-40
°
C to +125
°
C
Storage Temperature Range,
T
S
..............................
-55
°
C to +150
°
C
* Each output, all outputs on.
† Pulse duration
≤
100
µs,
duty cycle
≤
2%.
Caution: These CMOS devices have input
static protection (Class 3) but are still
susceptible to damage if exposed to extremely
high static electrical charges.
FEATURES
I
50 V Minimum Output Clamp Voltage
I
250 mA Output Current (all outputs simultaneously)
I
1.3
Ω
Typical
r
DS(on)
I
Low Power Consumption
I
Replacements for TPIC6273N and TPIC6273DW
Always order by complete part number:
Part Number
Package
A6273KA
20-pin DIP
A6273KLW
20-lead SOIC
R
θJA
55°C/W
70°C/W
R
θJC
25°C/W
17°C/W
6273
8-BIT LATCHED
DMOS POWER DRIVER
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, V
DD
............... 4.5 V to 5.5 V
High-Level Input Voltage, V
IH
............................
≥
0.85V
DD
Low-level input voltage, V
IL
.................................
≤0.15V
DD
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C, V
DD
= 5 V, t
ir
= t
if
≤
10 ns (unless otherwise
specified).
Limits
Characteristic
Logic Supply Voltage
Output Breakdown
Voltage
Off-State Output
Current
Static Drain-Source
On-State Resistance
Symbol
V
DD
V
(BR)DSX
I
DSX
Test Conditions
Operating
I
O
= 1 mA
V
O
= 40 V
V
O
= 40 V T
A
= 125°C
Min.
4.5
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ.
5.0
—
0.05
0.15
1.3
2.0
1.3
250
—
—
625
150
675
400
15
150
Max.
5.5
—
1.0
5.0
2.0
3.2
2.0
—
1.0
-1.0
—
—
—
—
100
300
Units
V
V
µA
µA
Ω
Ω
Ω
mA
µA
µA
ns
ns
ns
ns
µA
µA
r
DS(on)
I
O
= 250 mA, V
DD
= 4.5 V
I
O
= 250 mA, V
DD
= 4.5 V, T
A
= 125°C
I
O
= 500 mA, V
DD
= 4.5 V (see note)
Nominal Output
Current
Logic Input Current
I
O(nom)
I
IH
I
IL
V
DS(on)
= 0.5 V, T
A
= 85°C
V
I
= V
DD
= 5.5 V
V
I
= 0, V
DD
= 5.5 V
I
O
= 250 mA, C
L
= 30 pF
I
O
= 250 mA, C
L
= 30 pF
I
O
= 250 mA, C
L
= 30 pF
I
O
= 250 mA, C
L
= 30 pF
V
DD
= 5.5 V, Outputs OFF
V
DD
= 5.5 V, Outputs ON
Prop. Delay Time
t
PLH
t
PHL
Output Rise Time
Output Fall Time
Supply Current
t
r
t
f
I
DD(off)
I
DD(on)
Typical Data is at V
DD
= 5 V and is for design information only.
NOTE — Pulse test, duration
≤100 µs,
duty cycle
≤2%.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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