5675
14-BIT, 400MSPS
DIGITAL-TO-ANOALOG CONVERTER
Functional Block Diagram
F
EATURES
:
•
•
•
•
•
•
400-MSPS Update Rate
LVDS-Compatable Input Interface
Differential Scalable Current Outputs: 2mA to 20mA
On-Chip 1.2-V Reference
Single 3.3-V Supply Operation
Power Dissipation: 820 mW at f
CLK
= 400MHz,
f
O
= 70MHz
D
ESCRIPTION
:
Maxwell Technologies 5675 is a 14-bit resolution high-
speed digital to analog converter. The 5675 is designed
for high-speed digital data transmission in wired and
wireless communication systems. The 5675 has exce-
lent spurios free dynamic range (SFDR) at high interme-
diate frequencies.
The 5675 operates from a single-supply voltage of 3.3V.
Power dissipation is 820 mW at fclk = 400 MSPS, fout =
70MHz. The 5675 provides a nominal full-scale differen-
tial current output of 20mA, supporting both single-
ended and differential applications. Theoutput can be
directly fed to the load with no additional external output
buffered required.
Maxwell Technologies' patented R
AD
-P
AK
® packaging
technology incorporates radiation shielding in the micro-
circuit package. It eliminates the need for box shielding
while providing the required radiation shielding for a life-
time in orbit or space mission. In a GEO orbit, R
AD
-P
AK
®
provides greater than 100 krad(Si) radiation dose toler-
ance. This product is available with screening up to
Class S.
All data sheets are subject to change without notice
07.13.04 Rev 1X
1
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2004 Maxwell Technologies
All rights reserved.
14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter
5675
T
ABLE
1. P
INOUT
D
ESCRIPTION
P
IN
19, 41, 46, 47
20, 42, 45, 48
39
22
21
1, 3, 5, 7, 9, 13, 23
25, 27, 29, 31, 33, 35
2, 4, 6, 8, 10, 14, 24
26, 28, 30, 32, 34, 36
16, 18
38
15, 17
40
43
44
37
S
YMBOL
AGND
AVDD
BIASJ
CLK
CLKC
D9(13:0)A
D
ESCRIPTION
Analog Negative Supply Voltage (Ground)
Analog Positive Supply Voltage
Full-scale Output Current Bias
External Clock Input
Complementory External Clock Input
LVDS Positive Input, data bits 13 through 0
D13A is most significant data bit (MSB)
D0A is the least significant bit (LSB)
LVDS Positive Input, data bits 13 through 0
D13B is most significant data bit (MSB)
D0B is the least significant bit (LSB)
Digital Negative Supply Voltage (Ground)
D(13:0)B
DGND
DLLOFF
DVDD
EXTIO
IOUT1
IOUT2
SLEEP
Memory
High = DLL Off / Low = DLL On
Digital Positive Supply Voltage
Internal reference out put or external reference input. Requires a 0.1uf decou-
pling capacitor to groind when used as reference output.
DAC current output. Full scale when all inputs are set to 1. Connect reference
side DAC load resistors to AVDD
DAC complimentory current output. Full scale when all inputs are set to 0.
Connect reference side DAC load resistors to AVDD
Asynchronous hardware power down input. Active high. Internally pulldown.
T
ABLE
2. 5675 A
BSOLUTE
M
AXIMUM
R
ATINGS 1
P
ARAMETER
Supply Voltage Range
S
YMBOL
AV
DD
DV
DD
AV
DD
to DV
DD
Voltage between AGND and DGND
CLK, CLKC, SLEEP
Digital input D[13:0]A, D[13:0]B
IOUT1, IOUT2
EXTIO, BIASJ
Peak Input Current (any input)
Peak Total Input Current (any input)
Storage temperature range
07.13.04 Rev 1
M
IN
-0.3
-0.3
-3.6
-0.3
-0.3 to DVDD
-0.3 to DVDD
-1.0 to DVDD
-0.3 to DVDD
M
AX
3.6
3.6
3.6
0.5
DVDD to 0.3
DVDD to 0.3
AVDD to 0.3
AVDD to 0.3
20
-30
U
NIT
V
V
V
V
V
V
V
V
mA
mA
°
C
--
--
--
--
--
-65
150
All data sheets are subject to change without notice
2
©2004 Maxwell Technologies
All rights reserved.
14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter
T
ABLE
2. 5675 A
BSOLUTE
M
AXIMUM
R
ATINGS 1
P
ARAMETER
Operating Temperature range
S
YMBOL
M
IN
-55
M
AX
125
5675
U
NIT
°
C
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recom-
mended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
AVDD
I
DVDD
V
ARIATION
±10% of specified value in Table 5
±10% of specified value in Table 5
T
ABLE
4. 5675 R
ECOMMENDED
O
PERATING
C
ONDITIONS 1
P
ARAMETER
Output Update Rate
Analog Supply Voltage, AVDD
Digital Supply Voltage, DVDD
Input Reference Voltage, EXTIO
Full-scale output currentm IO(FS)
Output compliance range
Clock Pulse Width High, tWH
Clock Pulse Width Low, tLH
Clock Duty Cycle
40
AVDD=3.15 to 3.45V, IO(FS)=20mA
Clock Differential Input Votage, CLK-CLKC
DLL disable, DLLOFF=1
DLL enable, DLLOFF=0
100
3.15
3.15
0.6
2
AVDD-1
0.4
1.25
1.25
60
3.3
3.3
1.2
M
IN
T
YP
M
AX
100
400
3.6
3.6
1.25
20
AVDD+0.3
0.8
V
V
V
mA
V
V
nS
nS
%
U
NIT
MSPS
Memory
1. All unused control inputs of the device must be held at high or low ensure proper device operation.
T
ABLE
5. 5675 DC E
LECTRICAL
C
HARACTERISTICS
(DVDD = 3.3±10%, AVDD = 3.3±10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Resolution
DC Accuracy
1
Integral Nonlinearity
D
IFFERENTIAL
N
ONLINEARITY
M
ONOTICITY
07.13.04 Rev 1
T
EST
C
ONDITIONS
S
YMBLE
S
UBGROUPS
M
IN
14
T
YP
M
AX
U
NIT
Bits
T
MIN TO
T
MAX
T
MIN TO
T
MAX
INL
DNL
-4
-2
+2
+1.5
4
2
LSB
LSB
Monotonic 12-bit Level
All data sheets are subject to change without notice
3
©2004 Maxwell Technologies
All rights reserved.
14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter
T
ABLE
5. 5675 DC E
LECTRICAL
C
HARACTERISTICS
(DVDD = 3.3±10%, AVDD = 3.3±10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
A
NALOG
O
UTPUT
O
FFSET
E
RROR
G
AIN
E
RROR
O
UTPUT
R
ESISTANCE
O
UTPUT
C
APACITANCE
R
EFERENCE
O
UTPUT
R
EFERENCE
V
OLTAGE
R
EFERENCE
O
UTPUT
C
URRENT2
R
EFERENCE
I
NPUT
I
NPUT
R
ESISTANCE
S
MALL
S
IGNAL
B
ANDWIDTH
I
NPUT
C
APACITANCE
T
EMPERATURE
C
OEFFICIENTS
O
FFSET
D
RIFT
G
AIN
D
RIFT
R
EFERENCE
V
OLTAGE
D
RIFT
P
OWER
S
UPPLY
A
NALOG
S
UPPLY
C
URRENT3
D
IGITAL
S
UPPLY
C
URREN3T
A
NALOG
S
UPPLY
C
URRENT4
P
OWER
D
ISSIPATION
A
NALOG AND
D
IGITAL POWER
SUPPLY REJECTION RATIO
5675
M
IN
T
YP
M
AX
U
NIT
T
EST
C
ONDITIONS
S
YMBLE
S
UBGROUPS
0.02
Without Internal Reference
With Internal Reference
-10
-10
300
5
EXTIO
1.17
1.23
100
1
1.4
100
0
Without Internal Reference
V
EXTIO
+50
+50
1.29
10
10
%FSR
%FSR
%FSR
K
pf
V
nA
M
MHz
pf
Memory
ppm of
FSR/
°
C
ppm of
FSR/
°
C
ppm of
FSR/
°
C
I
AVDD
I
DVDD
Sleep Mode
AVdd = 3.3V, DVdd = 3.3V
AVdd = 3.15 to 3.45V
I
AVDD
P
D
A
PSRR
D
PSRR
See LVDS min/max
threshold voltage table
V
ITH
+
V
ITH
-
Z
T
C
I
90
-0.5
-0.5
175
100
45
0.5
0.5
100
-100
132
2
mA
mA
mA
%FSm
WR/V
LVDS I
NTERFACE
:
NODE
D[13:0]A; D[13:0]B
P
OSITIVE
-
GOING DIFFERENTIAL
INPUT VOLTAGE THRESHOLD
mV
N
EGATIVE
-
GOING DIFFERENTIAL
INPUT VOLTAGE THRESHOLD
I
NTERNAL
T
ERMINATION
I
MPEDANCE
I
NPUT
C
APACITANCE
CMOS I
NTERFACE
:
NODE
SLEEP
Ohms
pF
07.13.04 Rev 1
All data sheets are subject to change without notice
4
©2004 Maxwell Technologies
All rights reserved.
14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter
T
ABLE
5. 5675 DC E
LECTRICAL
C
HARACTERISTICS
(DVDD = 3.3±10%, AVDD = 3.3±10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
H
IGH
-L
EVEL INPUT VOLTAGE
L
OW
-L
EVEL INPUT VOLTAGE
H
IGH
-L
EVEL INPUT CURRENT
L
OW
-L
EVEL INPUT CURRENT
I
NPUT CAPACITANCE
C
LOCK INTERFACE
:
NODE
CLK, CLCKC
I
NPUT
R
ESISTANCE
I
NPUT
C
APACITANCE
I
NPUT
R
ESISTANCE
I
NPUT
C
APACITANCE
T
IMING
I
NPUT
S
ETUP
T
IME
I
NPUT
H
OLD
T
IME
I
NPUT
L
ATCH PULSE HIGH TIME
t
SU
t
h
TLPH
5675
M
IN
2
-10
-10
2
T
YP
3.3
0
0.8
10
10
M
AX
U
NIT
V
V
uA
uA
pF
Ohms
pF
Kohms
pF
nS
nS
nS
clk
T
EST
C
ONDITIONS
S
YMBLE
V
IH
V
IL
I
IH
I
IL
S
UBGROUPS
node CLK, CLKC
node CLK, CLKC
Differential
Differential
670
2
1.3
1
1.5
0.25
2
1
Memory
TDD
D
IGITAL
D
ELAY
T
IME
1. Measured Differential at IOUT1 and IOUT2. 2.5Ohms to AVDD
2. Use an external buffer amplifier with high impedance input drive to drive any external load.
3. Measured at f
CLK
= 400 MSPS and F
OUT
= 70 MHz
4. Measured for 50 Ohms Rl at IOUT1 and IOUT2, f
CLK
= 400 MSPS and f
OUT
= 70MHz
07.13.04 Rev 1
All data sheets are subject to change without notice
5
©2004 Maxwell Technologies
All rights reserved.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
