6595,6595 pdf中文资料,6595引脚图,6595电路-Datasheet-电子工程世界

6595

ADVANCE INFORMATION

(Subject to change without notice)

January 24, 2000

POWER

GROUND

LOGIC

SUPPLY

SERIAL

DATA IN

OUT

0

OUT

1

OUT

2

OUT

3

REGISTER

CLEAR

OUTPUT

ENABLE

POWER

GROUND

POWER

GROUND

LOGIC

GROUND

SERIAL

DATA OUT

OUT

7

OUT

6

OUT

5

OUT

4

CLOCK

STROBE

POWER

GROUND

8-BIT SERIAL-INPUT,

DMOS POWER DRIVER

The A6595KA and A6595KLW combine an 8-bit CMOS shift

register and accompanying data latches, control circuitry, and DMOS

power driver outputs. Power driver applications include relays, sole-

noids, and other medium-current or high-voltage peripheral power

loads.

The serial-data input, CMOS shift register and latches allow direct

interfacing with microprocessor-based systems. Serial-data input rates

are over 5 MHz. Use with TTL may require appropriate pull-up

resistors to ensure an input logic high.

A CMOS serial-data output enables cascade connections in appli-

cations requiring additional drive lines. Similar devices with reduced

r

DS(on)

are available as the A6A595.

The A6595 DMOS open-drain outputs are capable of sinking up to

750 mA. All of the output drivers are disabled (the DMOS sink drivers

turned off) by the OUTPUT ENABLE input high.

The A6595KA is furnished in a 20-pin dual in-line plastic package.

The A6595KLW is furnished in a wide-body, small-outline plastic

package (SOIC) with gull-wing leads. Copper lead frames, reduced

supply current requirements, and low on-state resistance allow both

devices to sink 150 mA from all outputs continuously, to ambient

temperatures over 85°C.

Data Sheet

26185.120

1

2

3

4

V

DD

20

19

18

17

REGISTER

LATCHES

5

6

7

8

9

10

CLR

OE

16

15

14

CLK

ST

13

12

11

Dwg. PP-029-13

Note that the A6595KA (DIP) and the A6595KLW (SOIC)

are electrically identical and share a common terminal

number assignment.

ABSOLUTE MAXIMUM RATINGS

at T

A

= 25

°

C

Output Voltage, V

O

...............................

50 V

Output Drain Current,

Continuous, I

O

..........................

250 mA*

Peak, I

OM

.................................

750 mA*†

Peak, I

OM

.......................................

2.0 A†

Single-Pulse Avalanche Energy,

E

AS

.................................................

75 mJ

Logic Supply Voltage, V

DD

..................

7.0 V

Input Voltage Range,

V

I

...................................

-0.3 V to +7.0 V

Package Power Dissipation,

P

D

...........................................

See Graph

Operating Temperature Range,

T

A

.................................

-40

°

C to +125

°

C

Storage Temperature Range,

T

S

.................................

-55

°

C to +150

°

C

* Each output, all outputs on.

† Pulse duration

≤

100

µs,

duty cycle

≤

2%.

Caution: These CMOS devices have input static

protection (Class 3) but are still susceptible to damage if

exposed to extremely high static electrical charges.

FEATURES

I

50 V Minimum Output Clamp Voltage

I

250 mA Output Current (all outputs simultaneously)

I

1.3

Ω

Typical

r

DS(on)

I

Low Power Consumption

I

Replacements for TPIC6595N and TPIC6595DW

Always order by complete part number:

Part Number

Package

A6595KA

20-pin DIP

A6595KLW

20-lead SOIC

R

θJA

55°C/W

70°C/W

R

θJC

25°C/W

17°C/W

6595

8-BIT SERIAL-INPUT,

DMOS POWER DRIVER

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

2.5

9

12

LOGIC SYMBOL

G3

C2

R

SRG8

C1

1D

2

4

5

6

A

2.0

SU

FF

IX

8

13

1.5

SU

FF

IX

'A

', R

θ

J

A

=

3

'LW

', R

55

°

C

/W

1.0

θ

J

=7

0

°

C/

W

7

14

0.5

15

16

0

25

50

75

100

125

AMBIENT TEMPERATURE IN

°C

150

2

17

18

Dwg. GS-004A

Dwg. FP-043

FUNCTIONAL BLOCK DIAGRAM

REGISTER

CLEAR

(ACTIVE LOW)

CLOCK

SERIAL

DATA IN

STROBE

OUTPUT

ENABLE

(ACTIVE LOW)

V

DD

LOGIC

SUPPLY

SERIAL

DATA OUT

SERIAL-PARALLEL SHIFT REGISTER

D-TYPE LATCHES

LOGIC

GROUND

POWER

GROUND

POWER

GROUND

OUT

0

OUT

N

Dwg. FP-013-5

Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

6595

8-BIT SERIAL-INPUT,

DMOS POWER DRIVER

VDD

IN

OUT

Dwg. EP-063-3

Dwg. EP-010-15

LOGIC INPUTS

DMOS POWER DRIVER OUTPUT

VDD

RECOMMENDED OPERATING CONDITIONS

over operating temperature range

Logic Supply Voltage Range, V

DD

............... 4.5 V to 5.5 V

High-Level Input Voltage, V

IH

............................

≥

0.85V

DD

Low-level input voltage, V

IL

.................................

≤0.15V

DD

OUT

Dwg. EP-063-2

SERIAL DATA OUT

TRUTH TABLE

Shift Register Contents

Data Clock

Input Input

H

L

X

I

0

H

L

I

1

I

2

...

…

I

6

I

7

Serial

Data

Output Strobe

R

6

R

6

R

7

X

P

7

—

R

0

R

1

R

2

P

0

P

1

P

2

X

L = Low Logic Level

H = High Logic Level

X = Irrelevant

X

…

R

6

R

7

P

6

P

7

X

L

H

P

0

P

1

P

2

H

…

P

6

P

7

H

Latch Contents

I

0

I

1

I

2

...

I

6

I

7

Output

Enable

I

0

Output Contents

I

1

I

2

…

I

6

I

7

R

0

R

1

R

0

R

1

R

5

R

6

R

5

R

6

R

6

R

7

X

R

0

R

1

R

2

X

P

0

P

1

P

2

P

6

P

7

P = Present State

R = Previous State

www.allegromicro.com

6595

8-BIT SERIAL-INPUT,

DMOS POWER DRIVER

ELECTRICAL CHARACTERISTICS at T

A

= +25

°

C, V

DD

= 5 V, t

ir

= t

if

≤

10 ns (unless otherwise

specified).

Limits

Characteristic

Output Breakdown

Voltage

Off-State Output

Current

Static Drain-Source

On-State Resistance

Symbol

V

(BR)DSX

I

DSX

Test Conditions

I

O

= 1 mA

V

O

= 40 V

V

O

= 40 V, T

A

= 125°C

Min.

50

—

I

OH

= -20

µA,

V

DD

= 4.5 V

I

OH

= -4 mA, V

DD

= 4.5 V

V

OL

I

OL

= 20

µA,

V

DD

= 4.5 V

I

OL

= 4 mA, V

DD

= 4.5 V

Prop. Delay Time

t

PLH

t

PHL

Output Rise Time

Output Fall Time

Supply Current

t

r

t

f

I

DD(OFF)

I

DD(ON)

I

DD(fclk)

I

O

= 250 mA, C

L

= 30 pF

I

O

= 250 mA, C

L

= 30 pF

I

O

= 250 mA, C

L

= 30 pF

I

O

= 250 mA, C

L

= 30 pF

All inputs low

V

DD

= 5.5 V, Outputs on

f

clk

= 5 MHz, C

L

= 30 pF, Outputs off

4.4

4.1

—

Typ.

—

0.05

0.15

1.3

2.0

1.3

250

—

1.3

4.49

4.3

0.002

0.2

650

150

7500

425

15

150

0.6

Max.

—

1.0

5.0

2.0

3.2

2.0

—

1.0

-1.0

—

0.1

0.4

—

100

300

5.0

Units

V

µA

Ω

mA

µA

V

ns

µA

mA

r

DS(on)

I

O

= 250 mA, V

DD

= 4.5 V

I

O

= 250 mA, V

DD

= 4.5 V, T

A

= 125°C

I

O

= 500 mA, V

DD

= 4.5 V (see note)

Nominal Output

Current

Logic Input Current

I

ON

I

IH

I

IL

V

DS(on)

= 0.5 V, T

A

= 85°C

V

I

= V

DD

= 5.5 V

V

I

= 0, V

DD

= 5.5 V

Logic Input Hysteresis

SERIAL-DATA

Output Voltage

V

I(hys)

V

OH

Typical Data is at V

DD

= 5 V and is for design information only.

NOTE — Pulse test, duration

≤100 µs,

duty cycle

≤2%.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

6595

8-BIT SERIAL-INPUT,

DMOS POWER DRIVER

TIMING REQUIREMENTS and SPECIFICATIONS

(Logic Levels are V

DD

and Ground)

C

CLOCK

A

SERIAL

DATA IN

DATA

t

p

SERIAL

DATA OUT

D

STROBE

50%

B

50%

DATA

E

OUTPUT

ENABLE

LOW = ALL OUTPUTS ENABLED

t

p

OUT

N

HIGH = OUTPUT OFF

50%

DATA

LOW = OUTPUT ON

Dwg. WP-029-2

HIGH = ALL OUTPUTS DISABLED

OUTPUT

ENABLE

50%

t

PLH

t

PHL

90%

t

f

DATA

t

r

OUT

N

10%

Dwg. WP-030-2

A.

Data Active Time Before Clock Pulse

(Data Set-Up Time), t

su(D)

..........................................

10 ns

B.

Data Active Time After Clock Pulse

(Data Hold Time), t

h(D)

..............................................

10 ns

C.

Clock Pulse Width, t

w(CLK)

.............................................

20 ns

D.

Time Between Clock Activation

and Strobe, t

su(ST)

.......................................................

50 ns

E.

Strobe Pulse Width, t

w(ST)

..............................................

50 ns

F.

Output Enable Pulse Width, t

w(OE)

................................

4.5

µ

s

NOTE – Timing is representative of a 12.5 MHz clock.

Higher speeds are attainable.

Serial data present at the input is transferred to the shift

register on the rising edge of the CLOCK input pulse. On

succeeding CLOCK pulses, the registers shift data information

towards the SERIAL DATA OUTPUT.

Information present at any register is transferred to the

respective latch on the rising edge of the STROBE input pulse

(serial-to-parallel conversion).

When the OUTPUT ENABLE input is high, the output

source drivers are disabled (OFF). The information stored in the

latches is not affected by the OUTPUT ENABLE input. With

the OUTPUT ENABLE input low, the outputs are controlled by

the state of their respective latches.

www.allegromicro.com

6595

6595概述

文档预览

推荐资源