5890
AND
5891
Frequently applied in non-impact printer systems, the UCN5890A,
UCN5890LW, UCN5891A, and UCN5891LW are BiMOS II serial-input,
latched source (high-side) drivers. The octal, high-current smart-power ICs
merge an 8-bit CMOS shift register, associated CMOS latches, and CMOS
control logic (strobe and output enable) with sourcing power Darlington
outputs. Typical applications include multiplexed LED and incandescent
displays, relays, solenoids, and similar peripheral loads to a maximum of
-500 mA per output.
BIMOS II 8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
GROUND
CLOCK
SERIAL
DATA IN
STROBE
OUT
1
OUT
2
OUT
3
OUT
4
1
2
3
4
5
6
7
8
ST
LATCHES
CLK
SHIFT
REGISTER
16
V
DD
15
OE
14
SERIAL
DATA OUT
LOGIC
SUPPLY
OUTPUT
ENABLE
LOAD
SUPPLY
OUT
8
OUT
7
OUT
6
OUT
5
Data Sheet
26182.12C
V
BB
13
12
11
10
9
Except for output voltage ratings, these smart high-side driver ICs are
equivalent. The UCN5890A/LW are rated for operation with load supply
voltages of 20 V to 80 V and a minimum output sustaining voltage of 50 V.
The UCN5891A/LW are optimized for operation with supply voltages of 5 V
to 50 V (35 V sustaining).
BiMOS II devices have higher data-input rates than the original BiMOS
circuits. With a 5 V supply, they will operate to at least 3.3 MHz. At 12 V,
higher speeds are possible. The CMOS inputs are compatible with standard
CMOS and NMOS logic levels. TTL circuits may require the use of appropri-
ate pull-up resistors to ensure a proper input-logic high. A CMOS serial data
output, allows cascading these devices in multiple drive-line applications
required by many dot matrix, alphanumeric, and bar graph displays.
Suffix ‘A’ devices are supplied in a standard dual in-line plastic package
with copper lead frame for enhanced package power dissipation characteris-
tics. Suffix ‘LW’ devices are supplied in a standard wide-body SOIC package
for surface-mount applications. Similar driver, featuring reduced output
saturation voltage, are the UCN5895A and A5895SLW. Complementary,
8-bit serial-input, latched sink drivers are the Series UCN5820A.
Dwg. PP-026-2A
Note the suffix ‘A’ devices (DIP) and the suffix
‘LW’ devices (SOIC) are electrically identical and
share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at T
A
= +25°C
Output Voltage, V
OUT
(UCN5890A & UCN5890LW) .........
80 V
(UCN5891A & UCN5891LW) .........
50 V
Logic Supply Voltage Range,
V
DD
....................................
4.5 V to 15 V
Driver Supply Voltage Range, V
BB
(UCN5890A/LW) ................
20 V to 80 V
(UCN5891A/LW) ...............
5.0 V to 50 V
Input Voltage Range,
V
IN
........................
-0.3 V to V
DD
+ 0.3 V
Continuous Output Current,
I
OUT
...........................................
-500 mA
Allowable Package Power Dissipation,
P
D
.........................................
See Graph
Operating Temperature Range,
T
A
..................................
-20
°
C to +85
°
C
Storage Temperature Range,
T
S
................................
-55
°
C to +150
°
C
Caution: CMOS devices have input static
protection, but are susceptible to damage when
exposed to extremely high static electrical
charges.
FEATURES
I
I
I
I
I
50 V or 80 V Source Outputs
Output Current to -500 mA
Output Transient-Suppression Diodes
To 3.3 MHz Data-lnput Rate
Low-Power CMOS Logic and Latches
Always order by complete part number, e.g., UCN5891LW .
5890
AND
5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
FUNCTIONAL BLOCK DIAGRAM
CLOCK
2.0
SUFFIX 'A', R
θJA
= 60°C/W
SERIAL
DATA IN
8-BIT SERIAL-PARALLEL SHIFT REGISTER
SERIAL
DATA OUT
1.5
STROBE
GROUND
LATCHES
VDD
1.0
MOS
BIPOLAR
OUTPUT
ENABLE
SUFFIX 'LW', R
0.5
θJA
= 80°C/W
VBB
0
25
50
75
100
125
AMBIENT TEMPERATURE IN
°C
150
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
Dwg. GP-018B
Dwg. No. A-12,654
TYPICAL INPUT CIRCUIT
VDD
Number of
Outputs On at
I
OUT
= -200 mA
8
7
6
5
4
3
2
1
UCN5890/91A Max. Allowable Duty Cycle
at T
A
of
50
°
C
53%
60%
70%
83%
100%
100%
100%
100%
60
°
C
47%
54%
64%
75%
94%
100%
100%
100%
70
°
C
41%
48%
56%
67%
84%
100%
100%
100%
IN
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
V
BB
Number of
Outputs On at
I
OUT
= -200 mA
OUT
UCN5890/91LW Max. Allowable Duty Cycle
at T
A
of
50
°
C
40%
45%
53%
62%
80%
100%
100%
100%
60
°
C
35%
41%
48%
56%
71%
96%
100%
100%
70
°
C
31%
36%
42%
50%
62%
84%
100%
100%
Dwg. No. A-12,648
8
7
6
5
4
3
2
1
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2000 Allegro MicroSystems, Inc.
5890
AND
5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C, V
BB
= 80 V (UCN5890A/LW) or 50 V
(UCN5891A/LW), V
DD
= 5 V and 12 V (unless otherwise noted).
Characteristic
Output Leakage Current
Symbol
I
CEX
V
CE(SAT)
V
BB
Max.
T
A
= +25°C
T
A
= +70°C
Output Saturation Voltage
50 V
I
OUT
= -100 mA
I
OUT
= -225 mA
I
OUT
= -350 mA
Output Sustaining Voltage
V
CE(sus)
V
IN(1)
V
IN(0)
Input Current
I
IN(1)
Z
IN
f
c
R
OUT
t
PLH
t
PHL
I
BB
l
DD
Max.
I
OUT
= -350 mA, L = 2 mH, UCN5891A/LW
I
OUT
= -350 mA, L = 2 mH, UCN5890A/LW
Input Voltage
50 V
V
DD
= 5.0 V
V
DD
= 12 V
50 V
50 V
V
DD
= 5 V to 12 V
V
DD
= V
IN
= 5.0 V
V
DD
= V
IN
= 12 V
Input lmpedance
50 V
V
DD
= 5.0 V
V
DD
= 12 V
Max. Clock Frequency
Serial Data Output
Resistance
Turn-On Delay
Turn-Off Delay
Supply Current
50 V
50 V
V
DD
= 5.0 V
V
DD
= 12 V
50 V
50 V
50 V
Output Enable to Output, I
OUT
= -350 mA
Output Enable to Output, I
OUT
= -350 mA
All outputs on, All outputs open
All outputs off
50 V
V
DD
= 5 V, All outputs off, Inputs = 0 V
V
DD
= 12 V, All outputs off, Inputs = 0 V
V
DD
= 5 V, One output on, All Inputs = 0 V
V
DD
= 12 V, One output on, All Inputs = 0 V
Diode Leakage Current
I
R
V
F
Max.
T
A
= +25°C
T
A
= +70°C
Diode Forward Voltage
Open
I
F
= 350 mA
Test Conditions
Min.
—
—
—
—
—
35
50
3.5
10.5
-0.3
—
—
100
50
3.3*
—
—
—
—
—
—
—
—
—
—
—
—
—
Limits
Max.
-50
-100
1.8
1.9
2.0
—
—
5.3
12.3
+0.8
50
240
—
—
—
20
6.0
2.0
10
10
200
100
200
1.0
3.0
50
100
2.0
Units
µA
µA
V
V
V
V
V
V
V
V
µA
µA
kΩ
kΩ
MHz
kΩ
kΩ
µs
µs
mA
µA
µA
µA
mA
mA
µA
µA
V
NOTES: Turn-off delay is influenced by load conditions. Systems applications well below the specified output loading may require
timing considerations for some designs, i.e., multiplexed displays or when used in combination with sink drivers in a totem
pole configuration.
Positive (negative) current is defined as going into (coming out of) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
www.allegromicro.com
5890
AND
5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
G
OUT
N
Dwg. No. A-12,649A
CLOCK
DATA IN
A
B
D
E
C
F
STROBE
BLANKING
TIMING REQUIREMENTS
(T
A
= +25°C,V
DD
= 5 V, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ..........................................................................
75 ns
B.
Minimum Data Active Time After Clock Pulse
(Data Hold Time) .............................................................................
75 ns
C.
Minimum Data Pulse Width ................................................................
150 ns
D.
Minimum Clock Pulse Width ...............................................................
150 ns
E.
Minimum Time Between Clock Activation and Strobe .......................
300 ns
F.
Minimum Strobe Pulse Width .............................................................
100 ns
G.
Typical Time Between Strobe Activation and
Output Transistion .........................................................................
500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the OUTPUT ENABLE input be high
during serial data entry.
When the OUTPUT ENABLE input is high,
all of the output buffers are disabled (off) without
affecting the information stored in the latches or
shift register. With the OUTPUT ENABLE input
low, the outputs are controlled by the state of
their respective latches.
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I
1
I
2
I
3
... I
N-1
I
N
H
L
X
H
L
R
1
R
2
...
R
1
R
2
...
R
N-2
R
N-1
R
N-2
R
N-1
R
N-1
R
N
X
X
Serial
Data Strobe
Output Input
R
N-1
R
N-1
R
N
X
P
N
X
L
H
X
R
1
R
2
R
3
...
P
1
P
2
P
3
...
... X X H
R
N-1
R
N
P
N-1
P
N
L
L
L
L
P
1
P
2
P
3
... P
N-1
P
N
... L
L
Latch Contents
I
1
I
2
I
3
...
I
N-1
I
N
Output
Enable
Output Contents
I
1
I
2
I
3
... I
N-1
I
N
R
1
R
2
R
3
...
X
X
X
...
P
1
P
2
P
3
...
P
N-1
P
N
X
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5890
AND
5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
TYPICAL APPLICATION
SOLENOID OR RELAY DRIVER
+5V
UCN5890A
1
16
SHIFT
REGISTER
+48V
DATA OUT
CLOCK
DATA IN
STROBE
2
3
4
5
6
7
8
V
DD
15
OE
14
13
12
11
10
9
OUTPUT ENABLE
(ACTIVE LOW)
LATCHES
V
BB
Dwg. No. A-12,548
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
www.allegromicro.com
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