PALCE16V8
PALCE16V8Z
COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25
COM’L:-25
IND:-12/15/25
PALCE16V8 and PALCE16V8Z Families
EE CMOS (Zero-Power) 20-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x
Pin and function compatible with all 20-pin PAL
®
devices
x
Electrically erasable CMOS technology provides reconfigurable logic and full testability
x
High-speed CMOS technology
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The
macrocells provide a universal device architecture. The PALCE16V8 will directly replace the
PAL16R8, with the exception of the PAL16C1.
The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALCE16V8Z allows battery-powered operation for an extended period.
The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
Publication#
16493
Amendment/0
Rev: F
Issue Date:
September 2000
U
SE
G
N AL
EW D
EV
D
ES IC
IG ES
N F
S O
R
x
x
x
x
x
x
x
x
x
x
x
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
Direct plug-in replacement for the PAL16R8 series
Outputs programmable as registered or combinatorial in any combination
Peripheral Component Interconnect (PCI) compliant
Programmable output polarity
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on power up
Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
Extensive third-party software and programmer support
Fully tested for 100% programming and functional yields and high reliability
5-ns version utilizes a split leadframe for improved performance
TYPICAL I
CC
CHARACTERISTICS
V
CC
= 5 V, T
A
= 25°C
150
125
16V8H-5
100
SE
G
N AL
EW D
EV
D
ES IC
IG ES
N F
S O
0
R
16V8H-7
16V8H-10
16V8H-15/25
16V8Z-12/15
16V8Q-10/15/25
I
CC
(mA)
75
50
16V8Z-25
25
U
0
10
20
30
Frequency (MHz)
40
50
16493E-9
I
CC
vs. Frequency
The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the
other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half
of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for I
CC
. From this midpoint, a designer may scale the I
CC
graphs up or down to
estimate the I
CC
requirements for a particular design.
PALCE16V8 and PALCE16V8Z Families
27
ENDURANCE CHARACTERISTICS
The PALCE16V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process.
This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the
device can be erased and reprogrammed—a feature which allows 100% testing at the factory.
Symbol
t
DR
N
Parameter
Min Pattern Data Retention Time
Max Operating Temperature
Min Reprogramming Cycles
Normal Programming Conditions
20
100
Years
Cycles
Test Conditions
Max Storage Temperature
Value
10
Unit
Years
ROBUSTNESS FEATURES
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE16V8
V
C
C
V
CC
SE
ESD
Protection
and
Clamping
G
N AL
EW D
EV
D
ES IC
IG ES
N F
S O
> 50 kΩ
Programming
Pins Only
Programming
Voltage
Detection
PALCE16V8X-X/5 devices have some unique features that make them extremely robust,
especially when operating in high-speed design environments. Pull-up resistors on inputs and
I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits
negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing.
A special noise filter makes the programming circuitry completely insensitive to any positive
overshoot that has a pulse width of less than about 100 ns for the /5 versions. Selected /4 devices
are also being retrofitted with these robustness features.
Positive
Overshoot
Filter
R
Programming
Circuitry
U
Typical Input
V
CC
V
CC
> 50 kΩ
Provides ESD
Protection and
Clamping
Preload Feedback
Circuitry
Input
16493E-10
Typical Output
28
PALCE16V8 and PALCE16V8Z Families
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