or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1003 Introduction_01.0
Lattice Semiconductor
Introduction
LA-MachXO Automotive Family Data Sheet
high-security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and
careful design will provide the high pin-to-pin performance also associated with CPLDs.
The ispLEVER
®
design tools from Lattice allow complex designs to be efficiently implemented using the LA-
MachXO automotive family of devices. Popular logic synthesis tools provide synthesis library support for LA-
MachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools
to place and route the design in the LA-MachXO device. The ispLEVER tool extracts the timing from the routing
and back-annotates it into the design for timing verification.
1-2
LA-MachXO Automotive Family Data Sheet
Architecture
February 2007
Data Sheet DS1003
Architecture Overview
The LA-MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO).
Some devices in this family have sysCLOCK PLLs and blocks of sysMEM™ Embedded Block RAM (EBRs). Fig-
ures 2-1, 2-2, and 2-3 show the block diagrams of the various family members.
The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a
column to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks.
The PIOs utilize a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of inter-
face standards. The blocks are connected with many vertical and horizontal routing channel resources. The place
and route software tool automatically allocates these routing resources.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional
unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register func-
tions. The PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and
PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic
blocks are arranged in a two-dimensional array. Only one type of block is used per row.
In the LA-MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on
different Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast
memory blocks; these blocks are found only in the larger devices. These blocks can be configured as RAM, ROM
or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT use.
The LA-MachXO architecture provides up to two sysCLOCK™ Phase Locked Loop (PLL) blocks on larger devices.
These blocks are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting
capabilities that are used to manage the frequency and phase relationships of the clocks.
Every device in the family has a JTAG Port that supports programming and configuration of the device as well as
access to the user logic. The LA-MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power
supplies, providing easy integration into the overall system.
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1003
Architecture_01.2
Lattice Semiconductor
Figure 2-1. Top View of the LA-MachXO1200 Device
1
Architecture
LA-MachXO Automotive Family Data Sheet
PIOs Arranged into
sysIO Banks
sysMEM Embedded
Block RAM (EBR)
Programmable
Functional Units
with RAM (PFUs)
Programmable
Functional Units
without RAM (PFFs)
sysCLOCK
PLL
JTAG Port
1. Top view of the LA-MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks.
瑞萨MCU/MPU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
