Si8440/1/2
Q
U A D
-C
H A N N E L
D
I G I TA L
I
S O L A T O R
Features
High-speed operation:
DC – 150 Mbps
Low propagation delay:
<10 ns
Wide Operating Supply Voltage:
2.375–5.5 V
Low power: I1 + I2 <
12 mA/channel at 100 Mbps
Precise timing:
2 ns pulse width distortion
1 ns channel-channel matching
2 ns pulse width skew
2500 V
RMS
isolation
Transient Immunity: >25 kV/µs
Tri-state outputs with ENABLE
control
DC correct
No start-up initialization required
<10 µs Startup Time
High temperature operation:
125 °C at 100 Mbps
100 °C at 150 Mbps
Wide body SOIC-16 package
Pin Assignments
Wide Body SOIC
V
DD1
GND1
A1
A2
A3
A4
EN1
GND1
1
2
3
4
5
6
7
8
Top View
16
15
14
13
12
11
10
9
V
DD2
GND2
B1
B2
B3
B4
EN2
GND2
Applications
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power factor correction systems
Safety Regulatory Approvals
UL recognition:2500 V
RMS
for 1
Minute per UL1577
CSA component acceptance
notice #5A
* All Pending
VDE certification conformity
DIN EN 60747-5-2 (VDE0884
Part 2):2003-01
DIN EN60950(VDE0805):
2001-12;EN60950:2000
V
IORM
= 560 V
PEAK
Description
Silicon Lab's family of digital isolators are CMOS devices that employ
an RF coupler to transmit digital information across an isolation
barrier. Very high speed operation at low power levels is achieved.
These parts are available in a 16-pin wide body SOIC package. Three
speed grade options (1, 10, 100 Mbps) are available and achieve
typical propagation delay of less than 10 ns.
Block Diagram
Si8440
Si8441
Si8442
A1
A2
A3
A4
NC
B1
B2
B3
B4
EN2
A1
A2
A3
A4
EN1
B1
B2
B3
B4
EN2
A1
A2
A3
A4
EN1
B1
B2
B3
B4
EN2
Rev. 0.3 4/06
Copyright © 2006 by Silicon Laboratories
Si8440/1/2
Si8440/1/2
T
A B L E
Section
OF
C
O N T E N TS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3. Enable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.4. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . . 17
4.5. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7. Package Outline: Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Rev. 0.3
3
Si8440/1/2
1. Electrical Specifications
Table 1. Electrical Characteristics
(V
DD1
= 5 V, V
DD2
= 5 V, T
A
= –40 to 125 C°)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Enable Input High Current
Enable Input Low Current
Si8440-A,-B,-C, V
DD1
Si8440-A,-B,-C, V
DD2
Si8440-A,-B,-C, V
DD1
Si8440-A,-B,-C, V
DD2
Si8441-A,-B,-C, V
DD1
Si8441-A,-B,-C, V
DD2
Si8441-A,-B,-C, V
DD1
Si8441-A,-B,-C, V
DD2
Si8442-A,-B,-C, V
DD1
Si8442-A,-B,-C, V
DD2
Si8442-A,-B,-C, V
DD1
Si8442-A,-B,-C, V
DD2
Si8440-B,-C, V
DD1
Si8440-B,-C, V
DD2
Si8441-B,-C, V
DD1
Si8441-B,-C, V
DD2
Si8442-B,-C, V
DD1
Si8442-B,-C, V
DD2
Si8440-C, V
DD1
Si8440-C, V
DD2
Si8441-C, V
DD1
Si8441-C, V
DD2
Si8442-C, V
DD1
Si8442-C, V
DD2
4
Symbol
V
IH
V
IL
V
OH
V
OL
I
L
I
ENH
I
ENL
Test Condition
Min
2.0
—
Typ
—
—
4.8
0.2
—
4
20
7.5
7
15
6.5
8.7
11
14
12.5
10
10
13
13
11
9
12
13.5
12.5
12.5
12
27
16
27
21
21
Max
—
0.8
—
0.4
±10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
V
V
V
V
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
loh = –4 mA
lol = 4 mA
V
ENx
= V
IH
V
ENx
= V
IL
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
V
DD1
,V
DD2
– 0.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC Supply Current
(All inputs 0 V or at Supply)
10 Mbps Supply Current
(All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
100 Mbps Supply Current
(All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Rev. 0.3
Si8440/1/2
Table 1. Electrical Characteristics (Continued)
(V
DD1
= 5 V, V
DD2
= 5 V, T
A
= –40 to 125 C°)
Parameter
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
1
Pulse Width Distortion
|t
PLH
- t
PHL
|
1
Symbol
Test Condition
Timing Characteristics
Min
0
—
Typ
—
5
7.5
1
6
0.5
2
2
30
30
5
5
3
Max
100
—
—
—
—
—
—
—
—
—
—
—
—
Unit
Mbps
ns
ns
ns
ns
ns
ns
ns
kV/µs
kV/µs
ns
ns
µs
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD/OD
C1 = 15 pF
C1 = 15 pF
CM
L
CM
H
t
en1
t
en2
t
SU
—
—
—
—
—
—
25
25
—
—
—
Propagation Delay Skew
2
Channel-Channel Skew
3
Output Rise Time
Output Fall Time
Common Mode Transient
Immunity at Logic Low Output
4
Common Mode Transient
Immunity at Logic High Output
4
Enable to Data Valid
Enable to Data Tri-State
Start-up Time
5
Notes:
1.
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling
edge of the V
Ox
signal. t
PLH
propagation delay is measured from the 50% level of the rising edge of the V
Ix
signal to the
50% level of the rising edge of the V
Ox
signal.
2.
t
PSK
is the magnitude of the worst-case difference in t
PHL
or t
PLH
that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
3.
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any
two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is
the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of
the isolation barrier.
4.
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is
the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
< 0.8 V. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range
over which the common mode is slewed.
5.
Start-up time is the time period from the application of power to valid data at the output.
ENABLE
INPUT
(V
IX
)
t
PLH
t
PHL
50%
OUTPUTS
OUTPUT
(V
OX
)
t
en1
t
en2
50%
Figure 1. ENABLE Timing Diagram
Figure 2. Propagation Delay Timing
Rev. 0.3
5
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