AN217
C8051F35
X
D
E L TA
-S
I G M A
ADC U
S E R
’
S
G
U I D E
Relevant Devices
This application note applies to the following devices:
C8051F350, C8051F351, C8051F352, C8051F353
1. Introduction
Delta-sigma analog-to-digital converters (ADCs) are oversampling ADCs: to reduce noise and analog front-end
circuit cost and complexity, they sample signals at very high rates and produce a low-noise, high-resolution output.
Oversampling at a “high” rate means sampling a signal at a frequency that is well above the bandwidth of interest’s
Nyquist rate and is done to lower in-band noise. The output word rate of the ADC will be close to the bandwidth of
interest.
Delta-sigma ADCs also add benefit by shaping noise and digitally filtering the information to enhance performance.
The oversampling, noise shaping, and digital filtering allow highly linear, high-resolution signal measurements, and
reduce the cost and complexity of circuits that must filter the signal at the input of the ADC.
Delta-sigma ADCs oversample a signal and produce relatively low output data rates and are best used in
applications requiring high precision measurements (16 to 24 bits) of low-bandwidth signals (i.e., typically 20 kHz
or less). Example applications include digital phones, temperature measurements, pressure measurements, and
weigh-scales. The maximum C8051F35x ADC output word rate is 1 kHz.
AV+
Input
Buffers
AIN+
AIN-
Σ
Voltage
Reference
SINC
3
Filter
Fast
Filter
PGA
Σ
Modulator
8-Bit
Offset
DAC
Figure 1. ADC0 Block Diagram
MDCLK
÷
SYSCLK
Rev. 0.2 2/05
Copyright © 2005 by Silicon Laboratories
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2. Using the C8051F35x Delta-Sigma ADC
Using delta-sigma ADCs require an understanding of how to properly configure the modulator, use of the digital
filter/decimator, and the nature of high-precision measurements of small signal voltages. Additionally, the
C8051F35x family of devices’ ADC provides functions such as calibration and offset adjustment that should be fully
understood when designing with these devices. The following sections describe the signal path from the input
signal source, to the ADC input, through the modulator, digital filter, and finally the output result (16- or 24-bit digital
output). Calibration of the ADC and circuit board design notes follow. Finally, delta-sigma noise specifications are
discussed.
2.1. Signal
The C8051F35x ADC is designed for optimal performance with a modulator sample rate of 19.2 kHz. The ADC is
designed as an oversampling data converter, so the bandwidth of the input signal should be low (the lower the
input signal bandwidth, the better the noise performance will be). The ADC is designed to measure voltages with
high precision.
2.1.1. Getting the Signal to the ADC
To aid high-precision measurements of small voltage signals, the ADC is best configured to input a differential
signal to an AIN+ and AIN– input pin pair. The analog multiplexer (AMUX) can select from eight external channels
of input, an on-chip temperature sensor, and an internal analog ground. The signal source (e.g, a transducer) can
be directly wired to the ADC’s input. If the input is from a pair of wires, twisted-pairs should be used with shielding
to reduce noise where feasible (keep wires as short as possible and away from other signals, especially digital
signals). The main idea is to design a system in which noise will be present equally on both AIN+ and AIN– in order
to reject common-mode noise. (See Figure 6 on page 12.)
2.1.2. Sensor Excitation
Some transducers require an excitation current to generate an output voltage. The C8051F35x devices feature two
on-chip current mode digital-to-analog converters (IDACs) for this purpose. See the data sheet for more details.
2.1.3. Analog Front-End
The input circuit to the ADC pins typically requires filtering and sometimes buffering and gain. Filtering
requirements for a delta-sigma ADC are low, and often the on-chip buffer and programmable gain will suffice.
2.1.4. External Buffer and Gain
The input signal must be kept within the dynamic range of the ADC (determined by the voltage reference voltage)
and within ground and supply voltage. The best measurement performance is achieved when the input signal’s
dynamic range is the same as the dynamic range of the ADC (i.e., voltage reference voltage). When the signal is
much smaller than the dynamic range of the ADC it will require amplification. The on-chip programmable gain or an
external amplifiercan can be used for this purpose. In many applications, a simple op-amp will suffice, but for best
performance choose a low-noise instrumentation or chopper stabilized amplifier.
Many sensors have high-impedance output stages and require a high-impedance input to avoid introducing offset
error. External amplifiers and op-amps serve this purpose. The C8051F35x devices also have an on-chip input
buffer. However, for very high-resolution measurements, the on-chip buffers or external op-amps may not suffice
due to drift (i.e., 1/f noise). For the best measurements, consider the use of chopper stabilized amplifiers (best for
high-accuracy dc measurements) or a low-noise amplifier.
2.1.5. Analog Input Filter
Typically, the only required input circuit needed for a delta-sigma ADC is an RC low-pass filter. While the ADC
shapes and filters noise, there is no noise rejection at the sample rate (19.2 kHz and its multiples). The RC time
constant should be designed to adequately remove noise at the sample rate frequency bandwidth, but not cause
error due to filter settling time as the input signal voltage changes. The ADC samples the signal at a high rate by
switching a capacitor. This results in average current flow into the ADC. This switching current can cause several
inaccuracies in measurement including gain and offset errors and non-linearity if the input filter is not properly
designed. Further, if an input buffer is used (e.g., an op-amp) the switched capacitor could result in amplifier
instability. The RC circuit solves these problems by providing isolation (the resistor) and a charge reservoir (the
capacitor).
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Resistor:
The resistor value should be high enough for isolation (i.e., at least 10s of ohms) but not too high to
cause settling time problems or gain errors. The gain error can be removed using the ADC’s calibration feature
(see the datasheet for details). When making a differential measurement, the input resistors to AIN+ and AIN–
must be matched to preserve common-mode rejection. It is typically more difficult to match higher valued
resistors.
Capacitor:
The capacitor acts as a charge reservoir (supplying the switched ADC sample capacitor) and as a
noise filter. Further, the ADC capacitor switching can be viewed as an average, steady input current. In reality,
the switching creates spikes of charging current that are highly non-linear as the modulator switches the ADC’s
sample capacitor. An external capacitor aids in linearizing the measurement. Electrolytic capacitors should not
be used because they will introduce distortion. Ceramic capacitors work well and should be sized large enough
such that a high valued resistor is not necessary. Typically, capacitors valued in the 1/10th’s of µF’s are used.
A corner frequency below the sample rate (19.2 kHz) is typically sufficient (e.g., R = 100
Ω
and C = 0.1 µF) for
most applications.
2.2. The ADC: Configuring the Delta-Sigma
1. Select
5. Configure
7. Calibrate
Input
Buffers
AIN+
Σ
Voltage
Reference
SINC
3
Filter
Fast Filter
PGA
Σ
AIN-
8-Bit
Offset
DAC
Modulator
6. Configure
4. Configure
3. Zero/Tare
2. Gain
Figure 2. Configuring The Delta-Sigma ADC
To achieve a high-resolution measurement, the delta-sigma ADC consists of two basic subsystems: the modulator
and the digital filter. One important concept to understand when configuring a delta-sigma data converter is that the
sample rate is much higher than the output rate of the ADC, so each sample does not result in an ADC output. The
signal is oversampled and then filtered to achieve the high-resolution measurement with reduced analog front-end
circuit requirements.
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3
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2.2.1. Voltage Reference
The voltage reference circuit should be treated as carefully as the measured signal, because noise on the voltage
reference degrades ADC performance. The C8051F35x can use its on-chip voltage reference (2.4 V typical) or an
externally supplied voltage reference (input to the VREF+ and VREF– pins). For optimal performance, we
recommend the use of a high-quality, low-noise external reference. To filter noise, use a 1.0 µF ceramic capacitor
connected between VREF+ and VREF–, placed as close to the pins as possible.
Note:
When using the internal voltage reference, VREF– must be connected to ground externally. This is typically done by con-
necting the VREF– pin directly to the analog ground plane.
2.2.2. Programmable Gain
The goal is to match the input signal dynamic range to the dynamic range that can be measured by the ADC
(based on voltage reference voltage). This can be accomplished by scaling the voltage reference (VREF) voltage
and by amplifying the signal. A larger VREF voltage improves performance, thus it is better to apply gain to the
signal rather than reducing VREF. A signal can be amplified using a combination of an external amplifier and/or the
internal programmable gain amplifier. (See “2.1.4. External Buffer and Gain” on page 2.)
The C8051F35x devices feature an on-chip programmable gain amplifier (PGA) with eight gain settings. The ADC
input gain is selected using the ADC0 Control Register (ADC0CN). ADC0CN[2:0] are the AD0GN bits used to
select one of the eight gain settings. (See SFR Definition 2.1.)
SFR Definition 2.1.
ADC0CN: ADC0 Control Register
R
R
R
R/W
R/W
R/W
Bit2
R/W
R/W
Bit0
SFR Address:
0xF4
Reset Value
-
Bit7
-
Bit6
-
Bit5
AD0POL
Bit4
AD0BCE
Bit3
AD0GN
Bit1
00010000
Bits 7–5: Unused: Read = 000b, Write = don’t care.
Bit 4:
AD0POL: ADC0 Polarity.
0: ADC operates in Unipolar mode (straight binary result).
1: ADC operates in Bipolar mode (2s compliment result).
Bit 3:
AD0BCE: ADC0 Burnout Current Source Enable.
0: ADC Burnout current sources disabled.
1: ADC Burnout current sources enabled.
Bits 2:0 AD0GN: ADC0 Programmable Gain Setting.
000: PGA Gain = 1.
001: PGA Gain = 2.
010: PGA Gain = 4.
011: PGA Gain = 8.
100: PGA Gain = 16.
101: PGA Gain = 32.
110: PGA Gain = 64.
111: PGA Gain = 128.
This SFR can only be modified when ADC0 is in IDLE mode.
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2.2.3. Offset DAC
The ADC features an internal dedicated DAC that is used to adjust the measurement offset of the ADC. This can
be used as a software controlled tare function in the end-product. For example, the offset DAC could be used to
remove the platform weight in a weigh scale application in order to measure only the scale contents of interest. The
offset DAC can make a signed adjustment to approximately ±1/2 of the ADC’s input range with any PGA gain
setting. See the “Offset DAC” section of the ADC0 chapter of the data sheet for complete information on how to
configure the offset DAC.
Note:
Small external system and ADC offset errors are corrected via the ADC’s built-in calibration function. The offset DAC is
used to zero or tare a measurement as a function of the end-product and is not intended for calibration.
2.2.4. Input Buffers
Two input buffers can be used to provide a high-impedance input to the ADC when a high-impedance sensor is
measured (i.e., the sensor will source very little current). One input buffer is used to measure signals with voltages
in the upper half of the voltage supply range (“high” input buffer) and one is used for the lower half of the voltage
supply range (“low” input buffer).
While the on-chip input buffers are adequate for many applications, they may not be sufficient for highly sensitive
measurements at the highest resolution (i.e, 24-bits). This is because they introduce 1/f noise, which will appear as
voltage “drift” in the measurement. For this reason, the input buffers can be bypassed, and an external buffer or
amplifier can be used. The input buffers are software controlled; therefore, they can easily be evaluated. See the
“Input Buffers” section of the ADC0 chapter of the data sheet for complete information and specifications for the
input buffers.
2.2.5. The Modulator
The modulator’s function is to oversample the measured signal, shape the noise such that it is reduced in the
signal bandwidth, and produce a series of 1-bit output codes. These output codes will have a density and order of
1s and 0s that are used to produce a high-resolution digital representation of the input signal (the modulator output
is digitally filtered to obtain large output words).
CLOCK (fs)
Analog
Input
INTEGRATOR
CLOCK (Kfs)
BIT
STREAM
LATCHED
COMPARATOR
(1-BIT ADC)
+
∑
-
1-BIT
DAC
+VREF
∫
DIGITAL
FILTER
DATA
-VREF
MODULATOR
Figure 3. Modulator and Digital Filter
In order to oversample the input signal and still obtain a reasonable output word rate, the modulator is configured
to operate at a high frequency. The modulator is designed with an integrator in a feedback loop. This integrator
shapes the noise so that the digital filter removes the maximum amount of the noise. This is the advantage of the
delta-sigma converter. To get this performance, it is important to configure the modulator to operate at its specified
frequency.
For the C8051F35x ADC, the modulator frequency should be 2.4576 MHz for optimum
performance.
The modulator clock (MDCLK) is derived from the MCU system clock. To allow flexibility in the use of many system
clock sources, the user has access to the divider in the ADC0 Modulator Clock Divisor (ADC0CLK) register (see
SFR Definition 2.2). The MDCLK value is set using the ADC0CLK register (see SFR Definition 2.2) to achieve a
frequency of 2.4576 MHz according to Equation 1:
MDCLK
=
(
SYSCLK
) ⁄ (
ADC0CLK
+
1
)
Equation 1. Configure Modulator Clock Frequency
Rev. 0.2
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PCB设计
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