PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
with reset and interrupt
Rev. 5 — 25 September 2014
Product data sheet
1. General description
The PCA9574 is a CMOS device that provides 8 bits of General Purpose parallel
Input/Output (GPIO) expansion in low voltage processor and handheld battery powered
mobile applications and was developed to enhance the NXP family of I
2
C-bus I/O
expanders. The improvements include lower supply current, lower operating voltage of
1.1 V to 3.6 V, dual and separate supply rails to allow voltage level translation anywhere
between 1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the
eight I/O ports can be configured as an input or output independent of each other and
default on start-up to inputs. I/O expanders provide a simple solution when additional I/Os
are needed while keeping interconnections to a minimum; for example in battery powered
mobile applications and clamshell devices for interfacing to sensors, push buttons,
keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of
a processor running at one voltage level to I/O devices operating at a different (usually
higher) voltage level. PCA9574 has built-in level shifting feature that makes these devices
extremely flexible in mixed signal environments where communication between
incompatible I/Os is required. The core of PCA9574 can operate at a voltage as low as
1.1 V while the I/O bank can operate in the range 1.1 V to 3.6 V. Bus-hold with
programmable on-chip pull-up or pull-down feature for I/Os is also provided.
The system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration register bits. The data for each input or output is kept in the corresponding
Input or Output register. The polarity of the read register can be inverted with the Polarity
inversion register (active HIGH or active LOW operation). Either a bus-hold function or
pull-up/pull-down feature can be selected by programming corresponding registers. The
bus-hold provides a valid logic level when the I/O bus is not actively driven. When
bus-hold feature is not selected, the I/O ports can be configured to have pull-up or
pull-down by programming the pull-up/pull-down configuration register.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is asserted
each time a change occurs on an input port unless that port is masked
(default = masked). A ‘GPIO All Call’ command allows programming multiple PCA9574s
at the same time even if they have different individual I
2
C-bus addresses. This allows
optimal code programming when more than one device needs to be programmed with the
same instruction or if all outputs need to be turned on or off at the same time. The internal
Power-On Reset (POR) or hardware reset pin (RESET) initializes the eight I/Os as inputs,
sets the registers to their default values and initializes the device state machine. The I/O
bank is held in its default state when the logic supply (V
DD
) is off.
One address select pin allows up to two PCA9574 devices to be connected with two
different addresses on the same I
2
C-bus.
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
The PCA9574 is available in TSSOP16 and HVQFN16 packages and is specified over the
40 C
to +85
C
industrial temperature range.
2. Features and benefits
400 kHz I
2
C-bus serial interface
Compliant with I
2
C-bus Standard-mode (100 kHz)
Separate supply rails for core logic and I/O bank provides voltage level shifting
1.1 V to 3.6 V operation with level shifting feature
Very low standby current: < 1
A
8 configurable I/O pins that default to inputs at power-up
Outputs:
Totem pole: 1 mA source and 3 mA sink
Independently programmable 100 k pull-up or pull-down for each I/O pin
Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs
Inputs:
Programmable bus hold provides valid logic level when inputs are not actively
driven
Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change or to prevent spurious interrupts default to mask at
power-up
Polarity inversion register allows inversion of the polarity of the I/O pins when read
Active LOW reset (RESET) input pin resets device to power-up default state
GPIO All Call address allows programming of more than one device at the same time
with the same parameters
2 programmable slave addresses using 1 address pin
40 C
to +85
C
operation
ESD protection exceeds 7000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: TSSOP16 and HVQFN16
3. Applications
PCA9574
Cell phones
Media players
Multi voltage environments
Battery operated mobile gadgets
Motherboards
Servers
RAID systems
Industrial control
Medical equipment
PLCs
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 25 September 2014
2 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
Gaming machines
Instrumentation and test measurement
4. Ordering information
Table 1.
Ordering information
Topside
marking
PCA9574
P74
Package
Name
TSSOP16
HVQFN16
Description
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3
3
0.85 mm
Version
SOT403-1
SOT758-1
Type number
PCA9574PW
PCA9574BS
4.1 Ordering options
Table 2.
Ordering options
Orderable part
number
Package
Packing method
Minimum order
quantity
Temperature range
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
Type number
PCA9574PW
PCA9574BS
PCA9574PW,118 TSSOP16
PCA9574BS,118 HVQFN16
Reel 13” Q1/T1
2500
*standard mark SMD
Reel 13” Q1/T1
6000
*standard mark SMD
5. Block diagram
PCA9574
A0
8-bit
SCL
SDA
INPUT
FILTER
I
2
C-BUS/SMBus
CONTROL
write pulse
read pulse
POWER-ON
RESET
INPUT/
OUTPUT
PORTS
V
DD(IO)
P0
P1
P2
P3
P4
P5
P6
P7
V
DD
V
DD
RESET
V
SS
LP
FILTER
002aad054
INT
Remark:
All I/Os are set to inputs at power-up and RESET.
Fig 1.
Block diagram of PCA9574
PCA9574
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 25 September 2014
3 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
data from
shift register
configuration
register
D
FF
Q
Q1
output port
register data
V
DD(IO)
data from
shift register
write
configuration
pulse
write pulse
CK
Q
D
FF
CK
Q
P0 to P7
Q2
output port
register
input port
register
D
FF
Q
ESD
protection
diode
V
SS
input port
register data
INTERRUPT
MASK
read pulse
V
DD(IO)
BUS-HOLD
AND
PULL-UP/PULL-DOWN
CONTROL
CK
to INT
100 kΩ
polarity
inversion
register
data from
shift register
write polarity
pulse
D
FF
CK
002aad066
Q
polarity
inversion
register data
Fig 2.
Simplified schematic of the I/Os (P0 to P7)
PCA9574
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 25 September 2014
4 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
6. Pinning information
6.1 Pinning
PCA9574BS
16 A0
terminal 1
index area
13 SDA
12 SCL
11 P7
10 P6
9
5
6
7
8
P5
P4
14 V
DD
V
DD(IO)
15 INT
V
SS
RESET
INT
A0
RESET
P0
P1
P2
P3
V
SS
1
2
3
4
5
6
7
8
002aad052
1
2
3
4
16 V
DD
15 SDA
14 SCL
P0
P1
P2
PCA9574PW
13 P7
12 P6
11 P5
10 P4
9
V
DD(IO)
P3
002aad053
Transparent top view
Fig 3.
Pin configuration for TSSOP16
Fig 4.
Pin configuration for HVQFN16
PCA9574
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 25 September 2014
5 of 32
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