MOSEL VITELIC
V54C3256164V
HIGH PERFORMANCE 3.3 VOLT
16M X 16 SYNCHRONOUS DRAM
4 BANKS X 4Mbit X 16
PRELIMINARY
-75
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Cycle Time (t
CK2
)
Clock Access Time (t
AC2
) CAS Latency = 2
133MHz
7.5 ns
5.4 ns
10 ns
6 ns
-8PC
125 MHz
8 ns
6 ns
10 ns
6 ns
-8
125 MHz
8 ns
6 ns
12 ns
6 ns
Features
s
4 banks x 4Mbit x 16 organization
s
High speed data transfer rates up to 133 MHz
s
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
s
Single Pulsed RAS Interface
s
Data Mask for byte Control
s
Four Banks controlled by BA0 & BA1
s
Programmable CAS Latency: 2, 3
s
Programmable Wrap Sequence: Sequential or
Interleave
s
Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
s
Multiple Burst Read with Single Write Operation
s
Automatic and Controlled Precharge Command
s
Random Column Address every CLK (1-N Rule)
s
Suspend Mode and Power Down Mode
s
Auto Refresh and Self Refresh
s
Refresh Interval: 8192 cycles/64 ms
s
Available in 54 Pin 400 mil TSOP-II
s
LVTTL Interface
s
Single +3.3 V
±
0.3 V Power Supply
s
-75 parts for PC133 3-3-3 operation
s
-8PC parts for PC100 2-2-2 operation
s
-8 parts for PC100 3-2-2 operation
Description
The V54C3256164V is a four bank Synchronous
DRAM organized as 4 banks x 4Mbit x 16. The
V54C3256164V achieves high speed data transfer
rates up to 133 MHz by employing a chip architec-
ture that prefetches multiple bits and then synchro-
nizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
133 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0
°
C to 70
°
C
Package Outline
T
•
Access Time (ns)
-75
•
Power
-8
•
-8PC
•
Std.
•
L
•
Temperature
Mark
Blank
V54C3256164V Rev. 1.1 January 2000
1
MOSEL VITELIC
V54C3256164V
Description
TSOP-II
Pkg.
T
Pin Count
54
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
V
CC
I/O
1
V
CCQ
I/O
2
I/O
3
V
SSQ
I/O
4
I/O
5
V
CCQ
I/O
6
I/O
7
V
SSQ
I/O
8
V
CC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
V
SS
I/O
16
V
SSQ
I/O
15
I/O
14
V
CCQ
I/O
13
I/O
12
V
SSQ
I/O
11
I/O
10
V
CCQ
I/O
9
V
SS
NC
UDQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Names
CLK
CKE
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356164V-01
CS
RAS
CAS
WE
A
0
–A
12
BA0, BA1
I/O
1
–I/O
16
LDQM, UDQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V54C3256164V Rev. 1.1 January 2000
2
MOSEL VITELIC
T
A
= 0 to 70
°
C, V
CC
= 3.3 V
±
0.3 V, f = 1 Mhz
Symbol Parameter
C
I1
C
I2
C
IO
C
CLK
Input Capacitance (A0 to A11)
Input Capacitance
RAS, CAS, WE, CS, CLK, CKE, DQM
Output Capacitance (I/O)
Input Capacitance (CLK)
V54C3256164V
Capacitance*
Max. Unit
5
5
pF
pF
6.5
4
pF
pF
*
Note:
Capacitance is sampled and not 100% tested.
Block Diagram
Column Addresses
A0 - A8, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
Bank 1
8192 x 512
x 16 bit
8192 x 512
x 16 bit
Column decoder
Sense amplifier & I(O) bus
8192 x 512
x 16 bit
Column decoder
Sense amplifier & I(O) bus
8192 x 512
x 16 bit
Input buffer
Output buffer
Control logic & timing generator
I/O
1
-I/O
16
WE
UDQM
CKE
RAS
CLK
CAS
CS
LDQM
V54C3256164V Rev. 1.1 January 2000
3
MOSEL VITELIC
Signal Pin Description
Pin
CLK
V54C3256164V
Type
Input
Signal
Pulse
Polarity
Positive
Edge
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
—
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
16M x 16 SDRAM CA0–CA8 (Page Length = 512 bits)
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
CS
Input
Pulse
RAS, CAS
WE
A0 - A12
Input
Pulse
Input
Level
BA0,
BA1
DQx
Input
Level
—
Selects which bank is to be active.
Input
Output
Input
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQM
LDQM
UDQM
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
LDQM and UDQM controls the lower and upper bytes in a x16 SDRAMs.
Power and ground for the input buffers and the core logic.
VCC, VSS Supply
VCCQ
VSSQ
Supply
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
V54C3256164V Rev. 1.1 January 2000
4
MOSEL VITELIC
Operation Definition
V54C3256164V
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Operation
Row Activate
Read
Read w/Autoprecharge
Write
Write with Autoprecharge
Row Precharge
Precharge All
Mode Register Set
No Operation
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Device
State
Idle
3
Active
3
Active
3
Active
3
Active
3
Any
Any
Idle
Any
Any
Idle
Idle
Idle
(Self Refr.)
Idle
Active
5
Any
(Power
Down)
Active
Active
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
H
CKE
n
X
X
X
X
X
X
X
X
X
X
H
L
CS
L
L
L
L
L
L
L
L
L
H
L
L
H
RAS
L
H
H
H
H
L
L
L
H
X
L
L
X
H
X
H
X
H
X
X
CAS
H
L
L
L
L
H
H
L
H
X
L
L
X
H
X
H
X
H
X
X
WE
H
H
H
L
L
L
L
L
H
X
H
H
X
X
X
X
X
L
X
X
DQM
X
X
X
X
X
X
X
X
X
X
X
X
A0-9,
A11
V
V
V
V
V
X
X
V
X
X
X
X
A10
V
L
H
L
H
L
H
V
X
X
X
X
BS0
BS1
V
V
V
V
V
V
X
V
X
X
X
X
L
H
L
H
X
X
X
X
Power Down Entry
H
L
L
H
X
X
X
X
Power Down Exit
L
H
L
X
X
X
X
X
X
Data Write/Output Enable
Data Write/Output Disable
H
H
X
X
L
H
X
X
X
X
X
X
Notes:
1. V = Valid , x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BS0, BS1 signals.
4. Device state is Full Page Burst operation
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle device is clock
suspend mode.
V54C3256164V Rev. 1.1 January 2000
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
