PRELIMINARY
W147G
Frequency Generator for Integrated Core Logic
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Three copies of CPU clock at 66/100 MHz
• Nine copies of 100-MHz SDRAM clocks
• Eight copies of PCI clock
• Two copies of synchronous APIC clock
• Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
• Two copies of 66-MHz fixed clock
• One copy of 14.31818-MHz reference clock
• Power-down control
• I
2
C interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............. 250 ps
APIC, 48MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ...................................................500 ps
APIC, 48MHz, SDRAM Output Skew: ......................... 250 ps
CPU, 3V66 Output Skew: ............................................175 ps
PCI Output Skew: ........................................................500 ps
CPU to SDRAM Skew (@ 100 MHz):................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns
PCI to APIC Skew: .....................................................±0.5 ns
Table 1. Pin Selectable Functions
SEL1
0
0
1
1
SEL0
0
1
0
1
Function
Three-state
Test
66-MHz CPU
100-MHz CPU
Block Diagram
VDDQ3
Pin Configuration
REF/APICDIV
VDDQ3
X1
X2
GND
GND
3V66_0
3V66_1
VDDQ3
VDDQ3
PCI0_ICH
PCI1
PCI2
GND
PCI3
PCI4
GND
PCI5
PCI6
PCI7
VDDQ3
VDD3
GND
GND
USB
DOT
VDDQ3
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
APIC0
APIC1
VDDQ2
CPU0
VDDQ2
CPU1
CPU2_ITP
GND
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
DCLK
VDDQ3
PWRDWN#
SCLK
SDATA
SEL1
X1
X2
XTAL
OSC
PLL REF FREQ
REF/APICDIV
VDDQ2
SDATA
SCLK
I
2
C
Logic
Divider,
Delay,
and
Phase
Control
Logic
2
CPU0:1
CPU2_ITP
APIC0:1
VDDQ3
W147G
2
SEL0:1
PLL 1
2
3V66_0:1
PCI0_ICH
7
PCI1:7
DCLK
PWRDWN#
8
SDRAM0:7
PLL2
VDDQ3
USB
DOT
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
October 13, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name
REF/APICDIV
Pin No.
1
Pin
Type
I/O
Pin Description
W147G
Reference Clock:
3.3V 14.318-MHz clock output. This pin doubles as the select
strap for APIC clock frequency. If strapped LOW during power up, APIC clock runs
at half PCI clock speed. Otherwise, APIC clocks run at PCI clock speed.
Crystal Input:
This pin has dual functions. It can be used as an external
14.318-MHz crystal connection as an external reference frequency input.
Crystal Output:
An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
PCI Clock 0 through 7:
3.3V 33-MHz PCI clock outputs. PCI1:7 can be individually
turned off via I
2
C interface.
66-MHz Clock Output:
3.3V fixed 66-MHz clock.
USB Clock Output:
3.3V fixed 48-MHz, non-spread spectrum USB clock outputs.
Dot Clock Output:
3.3V 48-MHz, non-spread spectrum signal.
Clock Function Selection pins:
LVTTL-compatible input to select device func-
tions. See
Table 1
for detailed descriptions.
Power Down Control:
LVTTL-compatible asynchronous input that places the de-
vice in power-down mode when held LOW.
CPU Clock Outputs:
Clock outputs for the host bus interface and integrated test
port. Output frequencies run at 66 MHz or 100 MHz depending on the configuration
of SEL0:1. Voltage swing set by V
DDQ2
.
SDRAM Clock Outputs:
3.3V outputs running at 100 MHz. SDRAM0:7 can be
individually turned off via I
2
C interface.
Sychronous APIC Clock Outputs:
Clock outputs running divide synchronous
with the PCI clock outputs. Output frequency is controlled by the strap option on
REF. Voltage swing set by V
DDQ2
.
Data pin for I
2
C circuitry.
Clock pin for I
2
C circuitry.
3.3V Power Connection:
Power supply for SDRAM output buffers, PCI output
buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
3.3V Power Connection:
Power supply for core logic, PLL circuitry. Connect to
3.3V.
2.5V Power Connection:
Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
Ground Connections:
Connect all ground pins to the common system ground
plane.
X1
X2
PCI0_ICH,
PCI1:7
3V66_0:1
USB
DOT
SEL0:1
PWRDWN#
CPU2_ITP,
CPU0:1
SDRAM0:7,
DCLK
APIC0:1
3
4
11, 12, 13, 15,
16, 18, 19. 20
7, 8
25
26
28, 29
32
49, 52, 50
I
I
O
O
O
O
I
I
O
46, 45, 43, 42,
40, 39, 37, 36,
34
55, 54
O
O
SDATA
SCLK
VDDQ3
30
31
2, 9, 10, 21, 27,
33, 38, 44
22
51, 53
5, 6, 14, 17, 23,
24, 35, 41, 47,
48, 56
I/O
I
P
VDD3
VDDQ2
GND
P
P
G
2
PRELIMINARY
V
DD
W147G
Output Strapping Resistor
Series Termination Resistor
Clock Load
10 kΩ
(Load Option 1)
W147G
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Q
Hold
Output
Low
D
10kΩ
(Load Option 0)
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W147G is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architec-
ture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
REF/APICDIV is a dual purpose l/O pin. Upon power-up the
pin acts as a logic input. If the pin is strapped to a LOW state
externally, APIC clock outputs will run divide synchronously at
half PCI clock speed. If it is pulled HIGH, APIC clock will run
synchronous to PCI clocks. An external 10-kΩ strapping resis-
tor should be used.
Figure 1
shows a suggested method for
strapping resistor connections.
Table 2. CK Whitney Truth Table
SEL1
0
0
1
1
SEL0
0
1
0
1
CPU
Hi-Z
TCLK/2
66 MHz
100 MHz
SDRAM
Hi-Z
TCLK/2
100 MHz
100 MHz
3V66
Hi-Z
TCLK/3
66 MHz
66 MHz
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below tar-
get but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Pin Selectable Functions
Table 1
outlines the device functions selectable through
SEL0:1. Specific outputs available at each pin is detailed in
Table 2
below. The SEL0 pin requires a 220Ω pull-up resistor
to 3.3V for the W147G to sense the maximum host bus fre-
quency of the processor and configure itself accordingly.
PCI
Hi-Z
TCLK/6
33 MHz
33 MHz
48MHz
Hi-Z
TCLK/2
48 MHz
48 MHz
REF
Hi-Z
TCLK
14.318 MHz
14.318 MHz
APIC
[1]
Hi-Z
TCLK/6
16.67 MHz
16.67 MHz
Notes
2
4, 5
3, 6, 7
3, 6, 7
Notes:
1. APIC clock frequency determined by the strap option on the REF/APICDIV input pin.
2. Provided for board level “bed of nails” testing.
3. “Normal” mode of operation.
4. TCLK is a test clock overdriven on the XTAL_IN input during test mode.
5. Required for DC output impedance verification.
6. Range of reference frequency allowed is: min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
3
PRELIMINARY
Offsets Among Clock Signal Groups
Figure 2
and
Figure 3
represent the phase relationship among
the different groups of clock outputs from W147G when it is
providing a 66-MHz CPU clock and a 100-MHz CPU clock,
10 ns
20 ns
W147G
respectively. It should be noted that when CPU clock is oper-
ating at 100 MHz, CPU clock output is 180 degrees out of
phase with SDRAM clock outputs.
0 ns
30 ns
40 ns
CPU 66-MHz
C PU 66 Pe riod
SDRAM 100-MHz
S D R A M 1 0 0 P erio d
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 33-MHz
Hu b-P CI
Figure 2. Group Offset Waveforms (66-MHz CPU Clock)
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 100-MHz
CP U 10 0 P eriod
SDRAM 100-MHz
SD R A M 10 0 P e rio d
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 33-MHz
H ub-P CI
Figure 3. Group Offset Waveforms (100-MHz CPU Clock)
4
PRELIMINARY
Power Down Control
W147G
W147G provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
0ns
25ns
50ns
75ns
Center
1
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
2
Figure 4. W147G PWRDWN# Timing Diagram
[8, 9, 10, 11]
Table 3. W147G Maximum Allowed Current
Max. 2.5V supply consumption
Max. discrete cap loads,
V
DDQ2
= 2.625V
All static inputs = V
DDQ3
or V
SS
100
µA
70 mA
100 mA
Max. 3.3V supply consumption
Max. discrete cap loads
V
DDQ3
= 3.465V
All static inputs = V
DDQ3
or V
SS
200
µA
280 mA
280 mA
W147
Condition
Powerdown Mode
(PWRDWN# = 0)
Full Active 66 MHz
SEL1,0 = 10 (PWRDWN# =1)
Full Active 100 MHz
SEL1,0 =11 (PWRDWN# = 1)
Notes:
8. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the next HIGH-to-LOW
transition.
9. PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W147G.
10. The shaded sections on the SDRAM, REF, and USB clocks indicate “don’t care” states.
11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
5
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