A3987
DMOS Microstepping Driver with Translator
Features and Benefits
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Low R
DS(on)
outputs
Short-to-ground protection
Shorted load protection
Automatic current decay mode detection/selection
Mixed and slow current decay modes
Synchronous rectification for low power dissipation
Internal UVLO and thermal shutdown circuitry
Crossover-current protection
Description
The A3987 is a complete microstepping motor driver with
built-in translator for easy operation. It is designed to operate
bipolar stepper motors in full, half, quarter, and sixteenth step
modes, with output drive capability of 50 V and
±1.5
A. The
A3987 includes a fixed off-time current regulator, which has
the ability to operate in slow or mixed decay modes.
The translator is the key to the easy implementation of the
A3987. Simply inputting one pulse on the step input drives the
motor to take one microstep. There are no phase sequence tables,
high frequency control lines, or complex interfaces to program.
The A3987 interface is an ideal fit for applications where a
complex microprocessor is unavailable or over-burdened.
The A3987 chopping control automatically selects the current
decay mode (slow or mixed). When a STEP signal occurs,
the translator determines if that step results in a higher or
lower current in each of the motor phases. If the change is to
a higher current, then the decay mode is set to slow decay. If
the change is to a lower current, then the decay mode is set to
30.1% fast decay. This current decay control scheme results
in reduced audible motor noise, increased step accuracy, and
reduced power dissipation.
Continued on the next page…
Package: 24 pin TSSOP with exposed
thermal pad (suffix LP)
Approximate scale
Typical Application Diagram
0.22
μF
VREG
10
μF
5 kΩ
Microcontroller or
Controller Logic
ROSC
STEP
DIR
SLEEP/RESET
ENABLE
MS1
MS2
REF
VDD
CP1
0.1
μF
X7R
CP2
VCP
0.1
μF
X7R
VBB1
A3987
VBB2
OUT1A
OUT1B
SENSE1
100
μF
OUT2A
OUT2B
SENSE2
3987DS, Rev.1
A3987
DMOS Microstepping Driver with Translator
protection. Special power-up sequencing is not required.
The A3987 is supplied in a thin profile (1.2 mm maximum height)
24-lead TSSOP (suffix LP) with exposed thermal tab. The package
is lead (Pb) free with 100% matte tin leadframe plating.
Description (continued)
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation.
Internal circuit protection includes: thermal shutdown with
hysteresis, undervoltage lockout (UVLO), and crossover current
Selection Guide
Part Number
A3987SLP-T
A3987SLPTR-T
Package
24-pin TSSOP with exposed thermal pad
24-pin TSSOP with exposed thermal pad
Packing
62 pieces / tube
3000 pieces / reel
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Output Current
Logic Supply Voltage
Logic Input Voltage Range
VBBx to OUTx
Sense Voltage
Reference Voltage
Nominal Operating Temperature
Maximum Junction Temperature
Storage Temperature
V
SENSE
V
REF
T
A
T
J
(max)
T
stg
Range S
Symbol
V
BB
I
OUT
V
DD
V
IN
Output current rating may be limited by duty cycle, ambient
temperature, and heat sinking. Under any set of conditions,
do not exceed the specified current rating or a junction tem-
perature of 150°C.
Notes
Rating
50
±1.5
7.0
–0.3 to V
DD
+ 0.3
50
0.5
0 to 4
–20 to 85
150
–55 to 150
Units
V
A
V
V
V
V
V
ºC
ºC
ºC
Thermal Characteristics*
Characteristic
Package Thermal Resistance
*Additional thermal data available on the Allegro website.
Maximum Power Dissipation, P
D
(max)
5.5
5.0
4.5
4.0
Symbol
R
θJA
Notes
4-layer PCB based on JEDEC standard
2-layer PCB with 3.8 in.
2
2 oz. copper each side
Rating
28
32
Units
°C/W
°C/W
Power Dissipation, P
D
(W)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
(R
θ
J
(R
θ
J
A
=
28
ºC
A
=
/W
32
)
ºC
/W
)
20
40
60
80
100
120
Temperature (°C)
140
160
180
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A3987
DMOS Microstepping Driver with Translator
Functional Block Diagram
0.22 µF
0.1 µF
CP1
CP2
VCP
VREG
VDD
Regulator
Charge
Pump
0.1 µF
To V
DD
DAC
V
REG
V
CP
PWM Latch
Blanking
Mixed Decay
DMOS Full Bridge 1
VBB1
OSC
ROSC
OUT1A
OUT1B
To V
DD
STEP
DIR
Translator
SLEEP/RESET
MS1
MS2
OUT2A
ENABLE
PWM Latch
Blanking
Mixed Decay
OUT2B
Gate
Drive
SENSE1
Control
Logic
OCP
DMOS Full Bridge 2
VBB2
SENSE2
DAC
Buffer
REF
GND
GND
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A3987
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS
1
valid at T
A
= 25°C, V
BB
= 50 V, unless noted otherwise
Characteristics
Output Drivers
Load Supply Voltage Range
Logic Supply Voltage Range
Output On Resistance
Body Diode Forward Voltage
V
BB
V
DD
R
DS(on)
V
F
Operating
During sleep mode
Operating
Source driver, I
OUT
= –1.5 A
Sink driver, I
OUT
= 1.5 A
Source diode, I
F
= –1.5 A
Sink diode, I
F
= 1.5 A
f
PWM
< 50 kHz
Motor Supply Current
I
BB
Operating, outputs disabled
Sleep (idle) mode
f
PWM
< 50 kHz
Logic Supply Current
Control Logic
Logic Input Voltage
Logic Input Current
Input Hysteresis
Blank Time
Fixed Offtime
Reference Input Voltage Range
Reference Input Current
GM Error
3
Crossover Dead Time
Reset Pulse Width
Sleep Pulse Width
UVLO Enable Threshold
UVLO Hysteresis
Continued on the next page…
I
REF
V
REF
= 4 V, DAC = 37.5%
Err
t
DT
t
RP
t
S
V
UVLO
V
UVHYS
V
DD
rising
V
REF
= 4 V, DAC = 70.31%
V
REF
= 4 V, DAC = 100%
t
BLANK
t
OFF
f
osc
= 4 MHz
ROSC tied to ground
R
OSC
= 59 KΩ
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
IN
= V
DD
× 0.7
V
IN
= V
DD
× 0.3
V
DD
× 0.7
–
–20
–20
150
0.7
15
23
0.8
–3
–
–
–
300
0.2
>2.5
2.35
0.05
–
–
<1.0
<1.0
–
1
25
30
–
0
–
–
–
650
–
–
2.7
0.10
–
V
DD
× 0.3
20
20
600
1.3
35
37
4
3
±15
±10
±5
900
1
–
3
–
V
V
μA
μA
mV
ms
ms
ms
V
mA
%
%
%
ns
μs
μs
V
V
I
DD
Outputs off
Sleep mode
8
0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
0.54
0.54
–
–
–
–
–
–
–
–
50
50
5.5
0.6
0.6
1.2
1.2
4
2
20
12
10
100
V
V
V
Ω
Ω
V
V
mA
mA
μA
mA
mA
μA
Symbol Test Conditions
Min.
Typ.
2
Max.
Units
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
A3987
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS
1
(continued)
valid at T
A
= 25°C, V
BB
= 50 V, unless noted otherwise
Characteristics
Protection Circuitry
Overcurrent Protection Threshold
4
Overcurrent Blanking
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
1
Negative
2
Typical
Symbol Test Conditions
Min.
Typ.
2
Max.
Units
I
ocpst
t
ocp
T
TSD
T
TSDhys
2
1
–
–
–
165
15
–
3
–
–
A
μs
°C
°C
current is defined as coming out of (sourcing) the specified device pin.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-
vidual units, within the specified maximum and minimum limits.
3
V
ERR
= [(V
REF
/ 8) – V
SENSE
] / (V
REF
/ 8).
4
OCP is tested at T = 25°C in a restricted range and guaranteed by characterization.
A
t
A
t
B
STEP
t
C
MS1, MS2,
RESET/SLEEP,
or DIR
t
D
Time Duration
STEP minimum, HIGH pulse width
STEP minimum, LOW pulse width
Setup time, input change to STEP
Hold time, input change to STEP
Figure 1. Logic Interface Timing Diagram
Symbol
t
A
t
B
t
C
t
D
Typ.
1
1
200
200
Unit
μs
μs
ns
ns
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
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