64Mb: x32
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Reduced output drive option
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, 8, or full page
• 32ms, 4,096-cycle auto refresh (7.8µs/cycle)
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• Programmable I/O (SSTL_2 compatible) – reduced
and impedance matched
MT46V2M32V1- 512K x 32 x 4 banks
MT46V2M32 - 512K x 32 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/dramds
PIN ASSIGNMENT (TOP VIEW)
100-Pin TQFP
(Normal Bend Shown)
DQ2
V
SS
Q
DQ1
DQ0
V
DD
V
DD
Q
DQS
NC \ RFU
V
SS
Q
DNU
NC
NC
NC
NC
V
DD
Q
V
SS
DQ31
DQ30
V
SS
Q
DQ29
OPTIONS
• Configuration
2 Meg x 32
(512K x 32 x 4 banks)
• Power Supply
2.5V V
DD
/V
DD
Q
2.65V V
DD
/V
DD
Q
• Plastic Package
100-pin TQFP (0.65mm lead pitch)
• Timing - Cycle Time
200 MHz @ CL = 3
183 MHz @ CL = 3
166 MHz @ CL = 3
150 MHz @ CL = 3
Part Number Example:
MARKING
2M32
V1
none
LG
DQ3
V
DD
Q
DQ4
DQ5
V
SS
Q
DQ6
DQ7
V
DD
Q
DQ16
DQ17
V
SS
Q
DQ18
DQ19
V
DD
Q
V
DD
V
SS
DQ20
DQ21
V
SS
Q
DQ22
DQ23
V
DD
Q
DM0
DM2
WE#
CAS#
RAS#
CS#
BA0
BA1
10099 98 97 96 95 94 93 9291 90 89 88 87 86 8584 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 3940 41 42 43 44 45 4647 48 49 50
DQ28
V
DD
Q
DQ27
DQ26
V
SS
Q
DQ25
DQ24
V
DD
Q
DQ15
DQ14
V
SS
Q
DQ13
DQ12
V
DD
Q
V
SS
V
DD
DQ11
DQ10
V
SS
Q
DQ9
DQ8
V
DD
Q
V
REF
DM3
DM1
CK
CK#
CKE
NC/MCL
A8/AP
Configuration
-5
-55
-6
-65
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
MT46V2M32V1LG-5
KEY TIMING PARAMETERS
SPEED
GRADE
CLOCK RATE
CL = 2**
125 MHz
100 MHz
100 MHz
100 MHz
CL = 3**
200 MHz
183 MHz
166 MHz
150 MHz
DATA-OUT
1.5ns
1.8ns
1.9ns
2.1ns
ACCESS
±0.75ns
±0.75ns
±0.75ns
±0.75ns
DQS-DQ
SKEW
+0.5ns
+0.5ns
+0.5ns
+0.5ns
WINDOW* WINDOW
64Mb (x32) DDR SDRAM PART NUMBER
PART NUMBER
MT46V2M32LG
ARCHITECTURE
2 Meg x 32
-5
-55
-6
-65
*Minimum clock rate @ CL = 3
**CL = CAS (Read) Latency
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
A0
A1
A2
A3
V
DD
A10
NC
NC
NC
NC
NC
NC
NC
NC
A9
V
SS
A4
A5
A6
A7
2 Meg x 32
512K x 32 x 4 banks
4K
2K (A0-A10)
4 (BA0, BA1)
256 (A0-A7)
64Mb: x32
DDR SDRAM
GENERAL DESCRIPTION
The 64Mb (x32) DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
67,108,864 bits. It is internally configured as a quad-
bank DRAM.
The 64Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 64Mb DDR SDRAM
effectively consists of a single 2n-bit wide, one-clock-
cycle data transfer at the internal DRAM core and two
corresponding
n-bit
wide, one-half-clock-cycle data
transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted ex-
ternally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
The 64Mb DDR SDRAM operates from a differential
clock (CK and CK#); the crossing of CK going HIGH and
CK# going LOW will be referred to as the positive edge
of CK. Commands (address and control signals) are
registered at every positive edge of CK. Input data is
registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE com-
mand are used to select the bank and the starting col-
umn location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, 8, or full page locations.
An auto precharge function may be enabled to provide
a self-timed row precharge that is initiated at the end of
the burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for con-
current operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2.
NOTE:
1. The functionality and the timing specifications
discussed in this data sheet are for the DLL-enabled
mode of operation.
2. Throughout the data sheet, the various figures and
text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise.
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
TABLE OF CONTENTS
Functional Block Diagram - 2 Meg x 32 ...................
Pin Descriptions ..........................................................
4
5
Random Writes .................................................
Write to Read - Uninterrupting ......................
Write to Read - Interrupting ...........................
Write to Read - Odd, Interrupting ..................
Write to Precharge - Uninterrupting .............
Write to Precharge - Interrupting ..................
Write to Precharge - Odd, Interrupting .........
Precharge ................................................................
Power-Down ...........................................................
Truth Table 2 (CKE)
......................................................
Truth Table 3 (Current State, Same Bank)
........................
Truth Table 4 (Current State, Different Bank)
..................
Operating Conditions
Absolute Maximum Ratings .......................................
DC Electrical and Operating Conditions ......................
AC Input Operating Conditions ................................
Clock Input Operating Conditions ...........................
Capacitance ..................................................................
I
DD
Specifications and Conditions .............................
AC Electrical Characteristics (Timing Table) ...........
Data Valid Window Derating .....................................
Voltage and Timing Waveforms
Nominal Output Drive Curves ............................
Reduced Output Drive Curves ............................
Output Timing -
t
DQSQ and
t
QH .........................
Output Timing -
t
AC and
t
DQSCK .......................
Input Timing ..........................................................
Input Voltage ..........................................................
Initialize and Load Mode Registers .....................
Power-Down Mode ................................................
Auto Refresh Mode ................................................
Self Refresh Mode ..................................................
Reads
Bank Read - Without Auto Precharge ............
Bank Read - With Auto Precharge ..................
Writes
Bank Write - Without Auto Precharge ...........
Bank Write - With Auto Precharge .................
Write - DM Operation ......................................
100-pin TQFP dimensions ..........................................
28
29
30
31
32
33
34
35
35
36
37
39
Functional Description
............................................... 7
Initialization ........................................................... 7
Register Definition ................................................ 7
Mode Register ................................................... 7
Burst Length ................................................ 7
Burst Type ................................................... 8
Read Latency ............................................... 9
Operating Mode .......................................... 9
Extended Mode Register ................................. 10
DLL Enable/Disable .................................. 10
Commands
...................................................................
Truth Table 1 (Commands)
............................................
Truth Table 1A (DM Operation)
......................................
Deselect ...................................................................
No Operation (NOP) ..............................................
Load Mode Register ...............................................
Active .......................................................................
Read .......................................................................
Write .......................................................................
Precharge ................................................................
Auto Precharge .......................................................
Burst Terminate .....................................................
Auto Refresh ...........................................................
Self Refresh .............................................................
Operation
.....................................................................
Bank/Row Activation .............................................
Reads .......................................................................
Read Burst .........................................................
Consecutive Read Bursts ................................
Nonconsecutive Read Bursts .........................
Random Read Accesses ...................................
Terminating a Read Burst ...............................
Read to Write .....................................................
Read to Precharge ............................................
Writes .......................................................................
Write Burst .........................................................
Consecutive Write to Write .............................
Non-consecutive Write to Write .....................
11
11
11
12
12
12
12
12
12
12
12
12
13
13
14
14
15
16
17
18
19
21
22
23
24
25
26
27
41
41
41
42
44
44
45
48
47
52
53
54
54
55
56
57
58
59
60
61
62
63
64
65
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
2 Meg x 32
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
COMMAND
DECODE
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTERS
REFRESH 11
COUNTER
13
11
ROW-
ADDRESS
MUX
11
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
2048
BANK0
MEMORY
ARRAY
(2048 x 256 x 32)
32
64
READ
LATCH
MUX
32
DQS
GENERATOR
CA0
32
CK
DATA
DLL
SENSE AMPLIFIERS
2048
DRVRS
1
DQ0 -
DQ31,
DM0 -
DM3
DQS
4
MASK
4
4
4
8
32
64
32
32
32
32
RCVRS
4
2
I/O GATING
DM MASK LOGIC
BANK
CONTROL
LOGIC
CA0
64
DQS
A0-A10,
BA0, BA1
13
ADDRESS
REGISTER
2
256
(x32)
64
WRITE
FIFO
&
DRIVERS
clk
out
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
7
1
clk
in DATA
8
CK
INPUT
REGISTERS
1
CA0
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
PIN DESCRIPTIONS
TQFP PIN NUMBERS
55, 54
SYMBOL
CK, CK#
TYPE
Input
DESCRIPTION
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE
in any bank). CKE is synchronous for POWER-DOWN entry and
exit, and for SELF REFRESH entry. CKE is asynchronous for SELF
REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after V
DD
is applied.
Chip Select: CS# enables (registered LOW) and disables (regis-
tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A8) for READ/
WRITE commands, to select one location out of the memory array
in the respective bank. A8 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
bank (A8 LOW, bank selected by BA0, BA1) or all banks (A8
HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Data Input/Output:
53
CKE
Input
28
CS#
Input
27, 26, 25
23, 56, 24, 57
RAS#, CAS#, Input
WE#
DM0-DM3 Input
29, 30
31-34, 47-51, 45, 36
BA0, BA1
Input
A0-A10
Input
97, 98, 100, 1, 3, 4, 6, 7
60, 61, 63, 64, 68, 69, 71, 72
9, 10, 12, 13, 17, 18, 20, 21
74, 75, 77, 78, 80, 81, 83, 84
DQ0-31
I/O
(continued on next page)
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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