2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
FLASH AND SRAM
COMBO MEMORY
FEATURES
• Flexible dual-bank architecture
• Support for true concurrent operations with no
latency:
Read bank
b
during program bank
a
and vice versa
Read bank
b
during erase bank
a
and vice versa
• Organization: 2,048K x 16 (Flash)
128K x 16 (SRAM)
• Basic configuration:
Flash
Bank
a
(4Mb Flash for data storage)
– Eight 4K-word parameter blocks
– Seven 32K-word blocks
Bank
b
(28Mb Flash for program storage)
– Fifty-six 32K-word main blocks
SRAM
2Mb SRAM for data storage
– 128K-words
• F_V
CC
, V
CC
Q, F_V
PP
, S_V
CC
voltages
1
1.65V (MIN)/1.95V (MAX) F_V
CC
read voltage or
1.80V (MIN)/2.20V (MAX) F_V
CC
read voltage
1.65V (MIN)/1.95V (MAX) S_V
CC
read voltage or
1.80V (MIN)/2.20V (MAX) S_V
CC
read voltage
1.65V (MIN)/1.95V (MAX) V
CC
Q or
1.80V (MIN)/2.20V (MAX) V
CC
Q
1.80V (TYP) F_V
PP
(in-system PROGRAM/ERASE)
0.0V (MIN)/2.20V (MAX) F_V
PP
(in-system
PROGRAM/ERASE)
2
12V ±5% (HV) F_V
PP
(production programming
compatibility)
• Asynchronous access time
1
Flash access time: 100ns or 110ns @ 1.65V F_V
CC
SRAM access time: 100ns @ 1.65V S_V
CC
• Page Mode read access
1
Interpage read access: 100ns/110ns @ 1.65V F_V
CC
Intrapage read access: 35ns/45ns @ 1.65V F_V
CC
• Low power consumption
• Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write SRAM during program/erase of Flash
• Dual 64-bit chip protection registers for security
purposes
• PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
MT28C3212P2FL
MT28C3212P2NFL
Low Voltage, Extended Temperature
BALL ASSIGNMENT
66-Ball FBGA (Top View)
1
A
B
C
D
E
F
G
H
NC
NC
NC
2
NC
3
A20
4
A11
5
A15
6
A14
7
A13
8
A12
9
F_V
SS
10
V
cc
Q
11
NC
12
NC
A16
A8
A10
A9
DQ15
S_WE#
DQ14
DQ7
F_WE#
NC
DQ13
DQ6
DQ4
DQ5
S_V
SS
F_RP#
DQ12
S_CE2
S_V
CC
F_V
CC
F_WP#
F_V
PP
A19
DQ11
DQ10
DQ2
DQ3
S_LB#
S_UB#
S_OE#
DQ9
DQ8
DQ0
DQ1
A18
A17
A7
A6
A3
A2
A1
S_CE1#
F_V
CC
A5
A4
A0
F_CE#
F_V
SS
F_OE#
NC
NC
NC
Top View
(Ball Down)
• Cross-compatible command set support
Extended command set
Common Flash interface (CFI) compliant
NOTE:
1. These specifications are guaranteed for operation
within either one of two voltage ranges, 1.65V–1.95V
or 1.80V–2.20V. Use only one of the two voltage
ranges for PROGRAM and ERASE operations.
2. MT28C3212P2NFL only.
OPTIONS
MARKING
• Timing
100ns
-10
110ns
-11
• Boot Block
Top
T
Bottom
B
• V
PP
1
Range
0.9V–2.2V
None
0.0V–2.2V
N
• Operating Temperature Range
Commercial Temperature (0
o
C to +70
o
C) None
Extended Temperature (-40
o
C to +85
o
C) ET
• Package
66-ball FBGA (8 x 8 grid)
FL
Part Number Example:
MT28C3212P2FL-10 TET
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
1
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
GENERAL DESCRIPTION
The MT28C3212P2FL and MT28C3212P2NFL com-
bination Flash and SRAM memory devices provide a
compact, low-power solution for systems where PCB
real estate is at a premium. The dual-bank Flash is a
high-performance, high-density, nonvolatile memory
device with a revolutionary architecture that can sig-
nificantly improve system performance.
This new architecture features:
• A two-memory-bank configuration supporting
dual-bank burst operation;
• A high-performance bus interface providing a fast
page data transfer; and
• A conventional asynchronous bus interface.
The device also provides soft protection for blocks
by configuring soft protection registers with dedicated
command sequences. For security purposes, dual 64-
bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). The WSM simplifies these operations
and relieves the system processor of secondary tasks.
An on-chip status register, one for each bank, can be
used to monitor the WSM status to determine the
progress of a PROGRAM/ERASE command.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation soft-
ware packages.
The device takes advantage of a dedicated power
source for the Flash device (F_V
CC
) and a dedicated
power source for the SRAM device (S_V
CC
), both at
1.65V–1.95V or 1.80V–2.20V for optimized power con-
sumption and improved noise immunity. The
MT28C3212P2FL and MT28C3212P2NFL devices sup-
port two V
PP
voltage ranges, V
PP
1
and V
PP
2
. V
PP
1
is an in-
circuit voltage of 0.9V–2.2V (MT28C3212P2FL) or 0.0V–
2.2V (MT28C3212P2NFL). V
PP
2
is the production com-
patibility voltage of 12V ±5%. The 12V ±5% V
PP
2
is sup-
ported for a maximum of 100 cycles and 10 cumulative
hours. See Table 1.
The MT28C3212P2FL and MT28C3212P2NFL de-
vices contain an asynchronous 2Mb SRAM organized
as 128K-words by 16 bits. These devices are fabricated
using an advanced CMOS process and high-speed/
ultra-low-power circuit technology.
The MT28C3212P2FL and MT28C3212P2NFL de-
vices are packaged in a 66-ball FBGA package with
0.80mm pitch.
DEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 2.
Table 1
V
PP
Voltage Ranges
DEVICE
MT28C3212P2FL
MT28C3212P2NFL
VOLTAGE RANGE
V
PP
1
V
PP
2
0.9V–2.2V 11.4V–12.6V
0.0V–2.2V 11.4V–12.6V
Table 2
Cross Reference for Abbreviated Device Marks
PART NUMBER
MT28C3212P2FL-10 BET
MT28C3212P2FL-10 TET
MT28C3212P2FL-11 BET
MT28C3212P2FL-11 TET
MT28C3212P2NFL-11 TET
PRODUCT
MARKING
FW443
FW442
FW444
FW433
FW445
SAMPLE
MARKING
FX443
FX442
FX444
FX433
FX445
MECHANICAL
SAMPLE MARKING
FY443
FY442
FY444
FY433
FY445
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
PART NUMBERING INFORMATION
Micron’s low-power devices are available with sev-
eral different combinations of features (see Figure 1).
Valid combinations of features and their correspond-
ing part numbers are listed in Table 3.
Figure 1
Part Number Chart
MT 28C 321 2 P 2 N FL-11 T ET
Micron Technology
Flash Family
28C = Dual-Supply Flash/SRAM Combo
Operating Temperature Range
None = Commercial (0ºC to +70ºC)
ET = Extended (-40ºC to +85ºC)
Boot Block Starting Address
B = Bottom boot
T = Top boot
Density/Organization/Banks
321 = 32Mb (2,048K x 16)
bank
a
= 1/8; bank
b
= 7/8
Access Time
-10 = 100ns
-11 = 110ns
SRAM Density
2 = 2Mb SRAM (128K x 16)
Package Code
Read Mode Operation
P = Asynchronous/Page Read
FL = 66-ball FBGA (8 x 8 grid)
V
PP1
Range
Operating Voltage Range
2 = 1.65V–1.95V or 1.80V–2.20V
None = 0.9V–2.2V
N = 0.0V–2.2V
Table 3
Valid Part Number Combinations
V
PP
1
RANGE
0.9V–2.2V
0.9V–2.2V
0.9V–2.2V
0.9V–2.2V
0.0V–2.2V
ACCESS
TIME (ns)
100
100
110
110
110
BOOT BLOCK
STARTING
ADDRESS
Bottom
Top
Bottom
Top
Top
OPERATING
TEMPERATURE
RANGE
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
PART NUMBER
MT28C3212P2FL-10 BET
MT28C3212P2FL-10 TET
MT28C3212P2FL-11 BET
MT28C3212P2FL-11 TET
MT28C3212P2NFL-11 TET
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
BLOCK DIAGRAM
F_WE#
F_OE#
F_CE#
F_RP#
A17
–
A20
F_V
CC
FLASH
F_V
PP
Bank
a
F_WP#
F_V
SS
2,048K x 16
Bank
b
V
CC
Q
DQ0
–
DQ15
SRAM
128K x 16
S_V
CC
A0
–
A16
S_CE1#
S_CE2
S_OE#
S_WE#
S_V
SS
S_UB#
S_LB#
FLASH FUNCTIONAL BLOCK DIAGRAM
PR Lock
PR Lock
Query
Query/OTP
OTP
DQ0-DQ15
X DEC
Data Input
Buffer
Data
Register
F_RST#
F_CE#
F_WE#
F_OE#
Program/
Erase
Pump Voltage
Generators
Output
Multiplexer
DQ0–DQ15
Y/Z DEC
Bank 1 Blocks
Y/Z Gating/Sensing
Manufacturer’s ID
Device ID
Block Lock
RCR
ID Reg.
CSM
Status
Reg.
WSM
I/O Logic
Output
Buffer
A0–A20
Address
Input
Buffer
Address
CNT/WSM
Address
Multiplexer
Y/Z DEC
X DEC
Y/Z Gating/Sensing
Bank 2 Blocks
Address Latch
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
BALL DESCRIPTIONS
66-BALL FBGA
NUMBERS
A3, A4, A5, A6,
A7, A8, B3, B4,
B5, B6, E5, G3,
G4, G5, G6, G7,
G8, G9, H4, H5,
H6
H7
H9
C3
D4
SYMBOL
A0–A20
TYPE
Input
DESCRIPTION
Address Inputs: Inputs for the addresses during READ and WRITE
operations. Addresses are internally latched during READ and WRITE
cycles. Flash: A0–A20; SRAM: A0–A16.
F_CE#
F_OE#
F_WE#
F_RP#
Input
Input
Input
Input
Flash Chip Enable: Activates the device when LOW. When CE# is HIGH,
the device is disabled and goes into standby power mode.
Flash Output Enable: Enables Flash output buffers when LOW. When
F_OE# is HIGH, the output buffers are disabled.
Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle.
F_WE# is active LOW.
Reset. When F_RP# is a logic LOW, the device is in reset, which drives
the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH,
the device is in standard operation. When F_RP# transitions from logic
LOW to logic HIGH, the device resets all blocks to locked and defaults to
the read array mode.
Flash Write Protect. Controls the lock down function of the flexible
locking feature.
SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level
deselects the SRAM and reduces the power consumption to standby
levels.
SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level
deselects the SRAM and reduces the power consumption to standby
levels.
SRAM Output Enable: Enables SRAM output buffers when LOW. When
S_OE# is HIGH, the output buffers are disabled.
SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle.
S_WE# is active LOW.
SRAM Lower Byte: When LOW, it selects the SRAM address lower byte
(DQ0–DQ7).
SRAM Upper Byte: When LOW, it selects the SRAM address upper byte
(DQ8–DQ15).
Data Inputs/Outputs: Input array data on the second CE# and WE#
cycle during PROGRAM command. Input commands to the command
user interface when CE# and WE# are active. Output data when CE#
and OE# are active.
E3
G10
F_WP#
S_CE1#
Input
Input
D8
S_CE2
Input
F5
B8
F3
F4
S_OE#
S_WE#
S_LB#
S_UB#
Input
Input
Input
Input
B7, B9, B10, DQ0–DQ15
Input/
C7, C8, C9,
Output
C10, D7, E6,
E8, E9, E10,
F7, F8, F9, F10
(continued on next page)
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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