INTEGRATED CIRCUITS
DATA SHEET
SAA5249
Integrated VIP and Teletext with
Background Memory Controller
(IVT1.1BMCX)
Preliminary specification
Supersedes data of December 1993
File under Integrated Circuits, IC02
1996 Nov 07
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller
FEATURES
•
Complete teletext decoder featuring a background
memory controller in a single 48-pin DIP package.
Capable of storing of up to 512 teletext pages in an
external DRAM, giving instant access to the teletext
data
•
Automatic processing of extension packet 26 for widest
possible language decoding. All our standard language
options can be available, and the language option is
readable via I
2
C-bus.
•
100% hardware compatible with the SAA5247 plug-in
replacement and with the possibility of extra market in
those countries with packet 26 transmissions.
Still pin-aligned to SAA5254 and SAA5244A.
•
100% software compatible with the SAA5247, and
SAA5244A, except if the special OSD symbols were
used. Also 100% software compatible to SAA5254. In all
events there is a change to the ROM ID number.
•
The device is pin-aligned with the other members of the
new Philips teletext decoder family, i.e. SAA5281 and
the SAA5254, making one hardware solution for the
whole range
•
Low software overhead for the microprocessor
•
RGB interface to standard colour decoder ICs, push-pull
output drive.
QUICK REFERENCE DATA
SYMBOL
V
DD
I
DD
V
syn
V
vid
f
XTAL
T
amb
supply voltage
supply current
sync amplitude
video amplitude
crystal frequency
operating ambient temperature
PARAMETER
−
0.1
0.7
−
−20
MIN.
4.5
TYP.
5.0
90
0.3
1.0
27
−
GENERAL DESCRIPTION
SAA5249
The Integrated VIP and Teletext (IVT1.1BMCX) is a
teletext decoder (contained within a single chip package)
for decoding 625-line based World System Teletext
transmissions. With its built-in background memory
controller the device can store incoming teletext packets in
the external 1M4 DRAM. With this large packet store
which can be rapidly scanned, we can achieve near
instantaneous access to all the pages transmitted by the
broadcaster.
This version of the decoder also contains some extra
hardware to process extension packet 26 automatically,
extending the markets to which the TV chassis can be
shipped and offering many more language options for the
set maker.
MAX.
5.5
120
0.6
1.4
−
+70
V
UNIT
mA
V
V
MHz
°C
ORDERING INFORMATION
TYPE
NUMBER
SAA5249P/E
SAA5249GP/E
PACKAGE
NAME
DIP48
QFP64
DESCRIPTION
plastic dual in-line package; 48 leads (600 mil)
plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14
×
20
×
2.7 mm; high stand-off height
VERSION
SOT240-1
SOT319-1
1996 Nov 07
2
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller
BLOCK DIAGRAM
SAA5249
A0 to A9
handbook, full pagewidth
D0 to D3
4
R/W
CAS0
CAS1 RAS
Y
BLANK
COR
RGBREF R/G/B
3
ODD/EVEN
10
46
45
42
SEL1
SEL2
23
24
41
29
21
27
DISPLAY
20
17 to 19
28
DRAM INTERFACE
VDD1
VDD2
V
SSn
3
12
16, 22
38
SAA5249
BACKGROUND
MEMORY
CONTROL
HAMMING
CHECKER
AND
PACKET 26
PROCESSING
ENGINE
MUX
DATA SLICER
AND
CLOCK
REGENERATOR
TELETEXT
ACQUISITION
AND
DECODING
PAGE
MEMORY
31
DCVBS
VSS1
REF+
7
8
ANALOG
TO
DIGITAL
CONVERTER
I C - BUS
INTERFACE
TIMING
CHAIN
2
SDA
SCL
30
OSCOUT
OSCIN
4
5
CRYSTAL
OSCILLATOR
INPUT CLAMP
AND
SYNC
SEPARATOR
9
11
10
CVBS
13
POL
15
DISPLAY
CLOCK
PHASE
LOCKED
LOOP
6
GNDO
14
STTV/LFB
MLB304
BLACK IREF
VCR/FFB
Fig.1 Block diagram for SOT240-1 (DIP48) package.
1996 Nov 07
3
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller
PINNING
PIN
SYMBOL
SOT240-1
n.c.
n.c.
V
DD1
OSCOUT
OSCIN
GNDO
V
SS1
REF+
BLACK
CVBS
IREF
V
DD2
POL
STTV/LFB
VCR/FFB
V
SS2
REF−
R
G
B
RGBREF
BLANK
V
SS3
CAS0
CAS1
A4
A3
COR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
−
17
18
19
20
21
22
23
24
25
26
27
SOT319-1
(1)
1
2
25
27
28
29
12
32
35
36
37
38
39
40
42
30
31
49
50
51
52
53
54, 55
56
57
58
59
60
not connected
not connected
+5 V supply
27 MHz crystal oscillator output
27 MHz crystal oscillator input
0 V crystal oscillator ground
0 V ground
DESCRIPTION
SAA5249
positive reference voltage; this pin should be connected to ground via a
100 nF capacitor
video black level storage pin; this pin should be connected to ground via a
100 nF capacitor
composite video input pin; a positive-going 1 V (p-p) input is required,
connected via a 100 nF capacitor
reference current input pin; connected to ground via a 27 kΩ resistor
+5 V supply
STTV/LFB/FFB polarity selection pin
sync to TV output pin/line flyback input pin; function controlled by an
internal register bit (scan sync mode)
PLL time constant switch/field input pin; function controlled by an internal
register bit (scan sync mode)
0 V ground
negative reference voltage; this pin should be connected to REF+ via a
100 nF capacitor
dot rate character output of the RED colour information
dot rate character output of the GREEN colour information
dot rate character output of the BLUE colour information
input DC voltage to define the output high level on the RGB pins
dot rate fast blanking output
0 V ground; internally connected for SOT319
column address select to external DRAM for BMCX function
column address select to external DRAM for BMCX function for second
DRAM where two 256 k
×
4 devices are used
address output to external DRAM for BMCX function
address output to external DRAM for BMCX function
programmable output to provide contrast reduction of the TV picture for
mixed text and picture displays or when viewing newsflash/subtitle pages;
open drain output
25 Hz output synchronized with the CVBS input field sync pulses to
produce a non-interlaced display by adjustment of the vertical deflection
currents
ODD/EVEN
28
61
1996 Nov 07
4
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller
PIN
SYMBOL
SOT240-1
Y
SCL
SDA
A5
A2
A6
A1
A7
A0
V
SS4
A8
A9
RAS
R/W
D2
D0
SEL2
SEL1
D3
D1
Note
1. The remaining pins for SOT319 are not connected.
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SOT319-1
(1)
62
63
64
4
5
6
8
9
11
43
13
14
15
18
19
20
21
22
23
24
DESCRIPTION
SAA5249
dot rate character output of teletext foreground colour information; open
drain output
serial clock input for I
2
C-bus; it can still be driven HIGH during power-down
of the device
serial data port for the I
2
C-bus; open drain output. It can still be driven
HIGH during power-down of the device
address output to external DRAM for BMCX function
address output to external DRAM for BMCX function
address output to external DRAM for BMCX function
address output to external DRAM for BMCX function
address output to external DRAM for BMCX function
address output to external DRAM for BMCX function
0 V ground
address output to external DRAM for BMCX function
address output to external DRAM for BMCX function
row address select to external DRAM
read/write for external DRAM
data input/output for external DRAM
data input/output for external DRAM
RAM select input to choose external DRAM size
RAM select input to choose external DRAM size
data input/output for external DRAM
data input/output for external DRAM
1996 Nov 07
5
DSP 与 ARM 处理器
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